2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/periph.h>
15 #include <asm/arch/pmu_rk3288.h>
16 #include <asm/arch/qos_rk3288.h>
17 #include <asm/arch/boot_mode.h>
19 #include <dm/pinctrl.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <power/regulator.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define PMU_BASE 0xff730000
27 static void setup_boot_mode(void)
29 struct rk3288_pmu *const pmu = (void *)PMU_BASE;
30 int boot_mode = readl(&pmu->sys_reg[0]);
32 debug("boot mode %x.\n", boot_mode);
35 writel(BOOT_NORMAL, &pmu->sys_reg[0]);
39 printf("enter fastboot!\n");
40 setenv("preboot", "setenv preboot; fastboot usb0");
43 printf("enter UMS!\n");
44 setenv("preboot", "setenv preboot; if mmc dev 0;"
45 "then ums mmc 0; else ums mmc 1;fi");
50 __weak int rk_board_late_init(void)
55 int rk3288_qos_init(void)
57 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
58 /* set vop qos to higher priority */
59 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
60 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
62 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
63 "rockchip,rk3288-tinker"))
65 /* set isp qos to higher priority */
66 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
67 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
68 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
73 int board_late_init(void)
78 return rk_board_late_init();
81 #ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
82 static int veyron_init(void)
88 ret = regulator_get_by_platname("vdd_arm", &dev);
90 debug("Cannot set regulator name\n");
94 /* Slowly raise to max CPU voltage to prevent overshoot */
95 ret = regulator_set_value(dev, 1200000);
98 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
99 ret = regulator_set_value(dev, 1400000);
102 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
104 ret = rockchip_get_clk(&clk.dev);
108 ret = clk_set_rate(&clk, 1800000000);
109 if (IS_ERR_VALUE(ret))
118 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
119 struct udevice *pinctrl;
123 * We need to implement sdcard iomux here for the further
124 * initlization, otherwise, it'll hit sdcard command sending
127 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
129 debug("%s: Cannot find pinctrl device\n", __func__);
132 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
134 debug("%s: Failed to set up SD card\n", __func__);
140 printf("board_init: Error %d\n", ret);
142 /* No way to report error here */
149 /* We do some SoC one time setting here */
150 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
166 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
168 debug("DRAM init failed: %d\n", ret);
171 ret = ram_get_info(dev, &ram);
173 debug("Cannot get DRAM size: %d\n", ret);
176 debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
177 gd->ram_size = ram.size;
182 #ifndef CONFIG_SYS_DCACHE_OFF
183 void enable_caches(void)
185 /* Enable D-cache. I-cache is already enabled in start.S */
190 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
192 #include <usb/dwc2_udc.h>
194 static struct dwc2_plat_otg_data rk3288_otg_data = {
200 int board_usb_init(int index, enum usb_init_type init)
204 bool matched = false;
205 const void *blob = gd->fdt_blob;
208 /* find the usb_otg node */
209 node = fdt_node_offset_by_compatible(blob, -1,
210 "rockchip,rk3288-usb");
213 mode = fdt_getprop(blob, node, "dr_mode", NULL);
214 if (mode && strcmp(mode, "otg") == 0) {
219 node = fdt_node_offset_by_compatible(blob, node,
220 "rockchip,rk3288-usb");
223 debug("Not found usb_otg device\n");
226 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
228 node = fdtdec_lookup_phandle(blob, node, "phys");
230 debug("Not found usb phy device\n");
234 phy_node = fdt_parent_offset(blob, node);
236 debug("Not found usb phy device\n");
240 rk3288_otg_data.phy_of_node = phy_node;
241 grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
243 /* find the grf node */
244 node = fdt_node_offset_by_compatible(blob, -1,
245 "rockchip,rk3288-grf");
247 debug("Not found grf device\n");
250 rk3288_otg_data.regs_phy = grf_phy_offset +
251 fdtdec_get_addr(blob, node, "reg");
253 return dwc2_udc_probe(&rk3288_otg_data);
256 int board_usb_cleanup(int index, enum usb_init_type init)
262 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
265 static const struct {
272 { "cpll", CLK_CODEC },
273 { "gpll", CLK_GENERAL },
274 #ifdef CONFIG_ROCKCHIP_RK3036
283 ret = rockchip_get_clk(&dev);
285 printf("clk-uclass not found\n");
289 for (i = 0; i < ARRAY_SIZE(clks); i++) {
294 ret = clk_request(dev, &clk);
298 rate = clk_get_rate(&clk);
299 printf("%s: %lu\n", clks[i].name, rate);
308 clock, 2, 1, do_clock,
309 "display information about clocks",
313 #define GRF_SOC_CON2 0xff77024c
315 int board_early_init_f(void)
317 struct udevice *pinctrl;
322 * This init is done in SPL, but when chain-loading U-Boot SPL will
323 * have been skipped. Allow the clock driver to check if it needs
326 ret = rockchip_get_clk(&dev);
328 debug("CLK init failed: %d\n", ret);
331 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
333 debug("%s: Cannot find pinctrl device\n", __func__);
337 /* Enable debug UART */
338 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
340 debug("%s: Failed to set up console UART\n", __func__);
343 rk_setreg(GRF_SOC_CON2, 1 << 0);