2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/periph.h>
15 #include <asm/arch/pmu_rk3288.h>
16 #include <asm/arch/qos_rk3288.h>
17 #include <asm/arch/boot_mode.h>
19 #include <dm/pinctrl.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <power/regulator.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define PMU_BASE 0xff730000
27 static void setup_boot_mode(void)
29 struct rk3288_pmu *const pmu = (void *)PMU_BASE;
30 int boot_mode = readl(&pmu->sys_reg[0]);
32 debug("boot mode %x.\n", boot_mode);
35 writel(BOOT_NORMAL, &pmu->sys_reg[0]);
39 printf("enter fastboot!\n");
40 setenv("preboot", "setenv preboot; fastboot usb0");
43 printf("enter UMS!\n");
44 setenv("preboot", "setenv preboot; if mmc dev 0;"
45 "then ums mmc 0; else ums mmc 1;fi");
50 __weak int rk_board_late_init(void)
55 int rk3288_qos_init(void)
57 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
58 /* set vop qos to higher priority */
59 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
60 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
62 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
63 "rockchip,rk3288-tinker"))
65 /* set isp qos to higher priority */
66 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
67 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
68 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
73 int board_late_init(void)
78 return rk_board_late_init();
81 #ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
82 static int veyron_init(void)
88 ret = regulator_get_by_platname("vdd_arm", &dev);
92 /* Slowly raise to max CPU voltage to prevent overshoot */
93 ret = regulator_set_value(dev, 1200000);
96 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
97 ret = regulator_set_value(dev, 1400000);
100 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
102 ret = rockchip_get_clk(&clk.dev);
106 ret = clk_set_rate(&clk, 1800000000);
107 if (IS_ERR_VALUE(ret))
116 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
117 struct udevice *pinctrl;
121 * We need to implement sdcard iomux here for the further
122 * initlization, otherwise, it'll hit sdcard command sending
125 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
127 debug("%s: Cannot find pinctrl device\n", __func__);
130 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
132 debug("%s: Failed to set up SD card\n", __func__);
138 printf("board_init: Error %d\n", ret);
140 /* No way to report error here */
147 /* We do some SoC one time setting here */
148 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
164 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
166 debug("DRAM init failed: %d\n", ret);
169 ret = ram_get_info(dev, &ram);
171 debug("Cannot get DRAM size: %d\n", ret);
174 debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
175 gd->ram_size = ram.size;
180 #ifndef CONFIG_SYS_DCACHE_OFF
181 void enable_caches(void)
183 /* Enable D-cache. I-cache is already enabled in start.S */
188 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
190 #include <usb/dwc2_udc.h>
192 static struct dwc2_plat_otg_data rk3288_otg_data = {
198 int board_usb_init(int index, enum usb_init_type init)
202 bool matched = false;
203 const void *blob = gd->fdt_blob;
206 /* find the usb_otg node */
207 node = fdt_node_offset_by_compatible(blob, -1,
208 "rockchip,rk3288-usb");
211 mode = fdt_getprop(blob, node, "dr_mode", NULL);
212 if (mode && strcmp(mode, "otg") == 0) {
217 node = fdt_node_offset_by_compatible(blob, node,
218 "rockchip,rk3288-usb");
221 debug("Not found usb_otg device\n");
224 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
226 node = fdtdec_lookup_phandle(blob, node, "phys");
228 debug("Not found usb phy device\n");
232 phy_node = fdt_parent_offset(blob, node);
234 debug("Not found usb phy device\n");
238 rk3288_otg_data.phy_of_node = phy_node;
239 grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
241 /* find the grf node */
242 node = fdt_node_offset_by_compatible(blob, -1,
243 "rockchip,rk3288-grf");
245 debug("Not found grf device\n");
248 rk3288_otg_data.regs_phy = grf_phy_offset +
249 fdtdec_get_addr(blob, node, "reg");
251 return dwc2_udc_probe(&rk3288_otg_data);
254 int board_usb_cleanup(int index, enum usb_init_type init)
260 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
263 static const struct {
270 { "cpll", CLK_CODEC },
271 { "gpll", CLK_GENERAL },
272 #ifdef CONFIG_ROCKCHIP_RK3036
281 ret = rockchip_get_clk(&dev);
283 printf("clk-uclass not found\n");
287 for (i = 0; i < ARRAY_SIZE(clks); i++) {
292 ret = clk_request(dev, &clk);
296 rate = clk_get_rate(&clk);
297 printf("%s: %lu\n", clks[i].name, rate);
306 clock, 2, 1, do_clock,
307 "display information about clocks",