2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rk3288.h>
15 #include <asm/arch/periph.h>
16 #include <asm/arch/pmu_rk3288.h>
17 #include <asm/arch/qos_rk3288.h>
18 #include <asm/arch/boot_mode.h>
20 #include <dm/pinctrl.h>
21 #include <dt-bindings/clock/rk3288-cru.h>
22 #include <power/regulator.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 __weak int rk_board_late_init(void)
31 int rk3288_qos_init(void)
33 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
34 /* set vop qos to higher priority */
35 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
36 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
38 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
39 "rockchip,rk3288-tinker"))
41 /* set isp qos to higher priority */
42 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
43 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
44 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
49 static void rk3288_detect_reset_reason(void)
51 struct rk3288_cru *cru = rockchip_get_cru();
57 switch (cru->cru_glb_rst_st) {
65 case FST_GLB_TSADC_RST_ST:
66 case SND_GLB_TSADC_RST_ST:
69 case FST_GLB_WDT_RST_ST:
70 case SND_GLB_WDT_RST_ST:
74 reason = "unknown reset";
77 env_set("reset_reason", reason);
80 * Clear cru_glb_rst_st, so we can determine the last reset cause
81 * for following resets.
83 rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
86 int board_late_init(void)
90 rk3288_detect_reset_reason();
92 return rk_board_late_init();
95 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
96 static int veyron_init(void)
102 ret = regulator_get_by_platname("vdd_arm", &dev);
104 debug("Cannot set regulator name\n");
108 /* Slowly raise to max CPU voltage to prevent overshoot */
109 ret = regulator_set_value(dev, 1200000);
112 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
113 ret = regulator_set_value(dev, 1400000);
116 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
118 ret = rockchip_get_clk(&clk.dev);
122 ret = clk_set_rate(&clk, 1800000000);
123 if (IS_ERR_VALUE(ret))
132 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
133 struct udevice *pinctrl;
137 * We need to implement sdcard iomux here for the further
138 * initlization, otherwise, it'll hit sdcard command sending
141 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
143 debug("%s: Cannot find pinctrl device\n", __func__);
146 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
148 debug("%s: Failed to set up SD card\n", __func__);
154 printf("board_init: Error %d\n", ret);
156 /* No way to report error here */
163 /* We do some SoC one time setting here */
164 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
174 #ifndef CONFIG_SYS_DCACHE_OFF
175 void enable_caches(void)
177 /* Enable D-cache. I-cache is already enabled in start.S */
182 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
184 #include <usb/dwc2_udc.h>
186 static struct dwc2_plat_otg_data rk3288_otg_data = {
192 int board_usb_init(int index, enum usb_init_type init)
196 bool matched = false;
197 const void *blob = gd->fdt_blob;
200 /* find the usb_otg node */
201 node = fdt_node_offset_by_compatible(blob, -1,
202 "rockchip,rk3288-usb");
205 mode = fdt_getprop(blob, node, "dr_mode", NULL);
206 if (mode && strcmp(mode, "otg") == 0) {
211 node = fdt_node_offset_by_compatible(blob, node,
212 "rockchip,rk3288-usb");
215 debug("Not found usb_otg device\n");
218 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
220 node = fdtdec_lookup_phandle(blob, node, "phys");
222 debug("Not found usb phy device\n");
226 phy_node = fdt_parent_offset(blob, node);
228 debug("Not found usb phy device\n");
232 rk3288_otg_data.phy_of_node = phy_node;
233 grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
235 /* find the grf node */
236 node = fdt_node_offset_by_compatible(blob, -1,
237 "rockchip,rk3288-grf");
239 debug("Not found grf device\n");
242 rk3288_otg_data.regs_phy = grf_phy_offset +
243 fdtdec_get_addr(blob, node, "reg");
245 return dwc2_udc_probe(&rk3288_otg_data);
248 int board_usb_cleanup(int index, enum usb_init_type init)
254 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
257 static const struct {
264 { "cpll", CLK_CODEC },
265 { "gpll", CLK_GENERAL },
266 #ifdef CONFIG_ROCKCHIP_RK3036
275 ret = rockchip_get_clk(&dev);
277 printf("clk-uclass not found\n");
281 for (i = 0; i < ARRAY_SIZE(clks); i++) {
286 ret = clk_request(dev, &clk);
290 rate = clk_get_rate(&clk);
291 printf("%s: %lu\n", clks[i].name, rate);
300 clock, 2, 1, do_clock,
301 "display information about clocks",
305 #define GRF_SOC_CON2 0xff77024c
307 int board_early_init_f(void)
309 struct udevice *pinctrl;
314 * This init is done in SPL, but when chain-loading U-Boot SPL will
315 * have been skipped. Allow the clock driver to check if it needs
318 ret = rockchip_get_clk(&dev);
320 debug("CLK init failed: %d\n", ret);
323 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
325 debug("%s: Cannot find pinctrl device\n", __func__);
329 /* Enable debug UART */
330 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
332 debug("%s: Failed to set up console UART\n", __func__);
335 rk_setreg(GRF_SOC_CON2, 1 << 0);