arch/arm/mach-rockchip/rk3288-board-spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  */
   5
   6 #include <common.h>
   7 #include <debug_uart.h>
   8 #include <dm.h>
   9 #include <fdtdec.h>
  10 #include <i2c.h>
  11 #include <led.h>
  12 #include <malloc.h>
  13 #include <ram.h>
  14 #include <spl.h>
  15 #include <asm/gpio.h>
  16 #include <asm/io.h>
  17 #include <asm/arch-rockchip/bootrom.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/periph.h>
  21 #include <asm/arch-rockchip/pmu_rk3288.h>
  22 #include <asm/arch-rockchip/sdram.h>
  23 #include <asm/arch-rockchip/sdram_common.h>
  24 #include <asm/arch-rockchip/sys_proto.h>
  25 #include <dm/root.h>
  26 #include <dm/test.h>
  27 #include <dm/util.h>
  28 #include <power/regulator.h>
  29 #include <power/rk8xx_pmic.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 u32 spl_boot_device(void)
  34 {
  35 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  36         const void *blob = gd->fdt_blob;
  37         struct udevice *dev;
  38         const char *bootdev;
  39         int node;
  40         int ret;
  41
  42         bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
  43         debug("Boot device %s\n", bootdev);
  44         if (!bootdev)
  45                 goto fallback;
  46
  47         node = fdt_path_offset(blob, bootdev);
  48         if (node < 0) {
  49                 debug("node=%d\n", node);
  50                 goto fallback;
  51         }
  52         ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev);
  53         if (ret) {
  54                 debug("device at node %s/%d not found: %d\n", bootdev, node,
  55                       ret);
  56                 goto fallback;
  57         }
  58         debug("Found device %s\n", dev->name);
  59         switch (device_get_uclass_id(dev)) {
  60         case UCLASS_SPI_FLASH:
  61                 return BOOT_DEVICE_SPI;
  62         case UCLASS_MMC:
  63                 return BOOT_DEVICE_MMC1;
  64         default:
  65                 debug("Booting from device uclass '%s' not supported\n",
  66                       dev_get_uclass_name(dev));
  67         }
  68
  69 fallback:
  70 #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
  71                 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
  72                 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
  73                 defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
  74         return BOOT_DEVICE_SPI;
  75 #endif
  76         return BOOT_DEVICE_MMC1;
  77 }
  78
  79 #if !defined(CONFIG_SPL_OF_PLATDATA)
  80 static int phycore_init(void)
  81 {
  82         struct udevice *pmic;
  83         int ret;
  84
  85         ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
  86         if (ret)
  87                 return ret;
  88
  89 #if defined(CONFIG_SPL_POWER_SUPPORT)
  90         /* Increase USB input current to 2A */
  91         ret = rk818_spl_configure_usb_input_current(pmic, 2000);
  92         if (ret)
  93                 return ret;
  94
  95         /* Close charger when USB lower then 3.26V */
  96         ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
  97         if (ret)
  98                 return ret;
  99 #endif
 100
 101         return 0;
 102 }
 103 #endif
 104
 105 __weak int arch_cpu_init(void)
 106 {
 107         return 0;
 108 }
 109
 110 #define TIMER_LOAD_COUNT_L      0x00
 111 #define TIMER_LOAD_COUNT_H      0x04
 112 #define TIMER_CONTROL_REG       0x10
 113 #define TIMER_EN        0x1
 114 #define TIMER_FMODE     BIT(0)
 115 #define TIMER_RMODE     BIT(1)
 116
 117 void rockchip_stimer_init(void)
 118 {
 119         /* If Timer already enabled, don't re-init it */
 120         u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
 121
 122         if (reg & TIMER_EN)
 123                 return;
 124
 125         asm volatile("mcr p15, 0, %0, c14, c0, 0"
 126                      : : "r"(COUNTER_FREQUENCY));
 127
 128         writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
 129         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
 130         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
 131         writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
 132                TIMER_CONTROL_REG);
 133 }
 134
 135 void board_init_f(ulong dummy)
 136 {
 137         struct udevice *dev;
 138         int ret;
 139
 140 #ifdef CONFIG_DEBUG_UART
 141         /*
 142          * Debug UART can be used from here if required:
 143          *
 144          * debug_uart_init();
 145          * printch('a');
 146          * printhex8(0x1234);
 147          * printascii("string");
 148          */
 149         debug_uart_init();
 150         debug("\nspl:debug uart enabled in %s\n", __func__);
 151 #endif
 152         ret = spl_early_init();
 153         if (ret) {
 154                 debug("spl_early_init() failed: %d\n", ret);
 155                 hang();
 156         }
 157
 158         /* Init secure timer */
 159         rockchip_stimer_init();
 160         /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
 161         timer_init();
 162
 163         arch_cpu_init();
 164
 165         ret = rockchip_get_clk(&dev);
 166         if (ret) {
 167                 debug("CLK init failed: %d\n", ret);
 168                 return;
 169         }
 170
 171 #if !defined(CONFIG_SPL_OF_PLATDATA)
 172         if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
 173                 ret = phycore_init();
 174                 if (ret) {
 175                         debug("Failed to set up phycore power settings: %d\n",
 176                               ret);
 177                         return;
 178                 }
 179         }
 180 #endif
 181
 182 #if !defined(CONFIG_SUPPORT_TPL)
 183         debug("\nspl:init dram\n");
 184         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 185         if (ret) {
 186                 debug("DRAM init failed: %d\n", ret);
 187                 return;
 188         }
 189 #endif
 190
 191 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
 192         back_to_bootrom(BROM_BOOT_NEXTSTAGE);
 193 #endif
 194 }
 195
 196 static int setup_led(void)
 197 {
 198 #ifdef CONFIG_SPL_LED
 199         struct udevice *dev;
 200         char *led_name;
 201         int ret;
 202
 203         led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
 204         if (!led_name)
 205                 return 0;
 206         ret = led_get_by_label(led_name, &dev);
 207         if (ret) {
 208                 debug("%s: get=%d\n", __func__, ret);
 209                 return ret;
 210         }
 211         ret = led_set_on(dev, 1);
 212         if (ret)
 213                 return ret;
 214 #endif
 215
 216         return 0;
 217 }
 218
 219 void spl_board_init(void)
 220 {
 221         int ret;
 222
 223         ret = setup_led();
 224         if (ret) {
 225                 debug("LED ret=%d\n", ret);
 226                 hang();
 227         }
 228
 229         preloader_console_init();
 230 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 231         back_to_bootrom(BROM_BOOT_NEXTSTAGE);
 232 #endif
 233         return;
 234 }
 235
 236 #ifdef CONFIG_SPL_OS_BOOT
 237
 238 #define PMU_BASE                0xff730000
 239 int dram_init_banksize(void)
 240 {
 241         struct rk3288_pmu *const pmu = (void *)PMU_BASE;
 242         size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
 243
 244         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 245         gd->bd->bi_dram[0].size = size;
 246
 247         return 0;
 248 }
 249 #endif