2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <debug_uart.h>
18 #include <asm/arch/bootrom.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/periph.h>
22 #include <asm/arch/pmu_rk3288.h>
23 #include <asm/arch/sdram.h>
24 #include <asm/arch/sdram_common.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
27 #include <dm/pinctrl.h>
31 #include <power/regulator.h>
32 #include <power/rk8xx_pmic.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 u32 spl_boot_device(void)
38 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
39 const void *blob = gd->fdt_blob;
45 bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
46 debug("Boot device %s\n", bootdev);
50 node = fdt_path_offset(blob, bootdev);
52 debug("node=%d\n", node);
55 ret = device_get_global_by_of_offset(node, &dev);
57 debug("device at node %s/%d not found: %d\n", bootdev, node,
61 debug("Found device %s\n", dev->name);
62 switch (device_get_uclass_id(dev)) {
63 case UCLASS_SPI_FLASH:
64 return BOOT_DEVICE_SPI;
66 return BOOT_DEVICE_MMC1;
68 debug("Booting from device uclass '%s' not supported\n",
69 dev_get_uclass_name(dev));
73 #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
74 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
75 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
76 return BOOT_DEVICE_SPI;
78 return BOOT_DEVICE_MMC1;
81 u32 spl_boot_mode(const u32 boot_device)
83 return MMCSD_MODE_RAW;
86 #ifdef CONFIG_SPL_MMC_SUPPORT
87 static int configure_emmc(struct udevice *pinctrl)
89 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
91 struct gpio_desc desc;
94 pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
97 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
98 * use the EMMC_PWREN setting.
100 ret = dm_gpio_lookup_name("D9", &desc);
102 debug("gpio ret=%d\n", ret);
105 ret = dm_gpio_request(&desc, "emmc_pwren");
107 debug("gpio_request ret=%d\n", ret);
110 ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
112 debug("gpio dir ret=%d\n", ret);
115 ret = dm_gpio_set_value(&desc, 1);
117 debug("gpio value ret=%d\n", ret);
125 #if !defined(CONFIG_SPL_OF_PLATDATA)
126 static int phycore_init(void)
128 struct udevice *pmic;
131 ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
135 #if defined(CONFIG_SPL_POWER_SUPPORT)
136 /* Increase USB input current to 2A */
137 ret = rk818_spl_configure_usb_input_current(pmic, 2000);
141 /* Close charger when USB lower then 3.26V */
142 ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
151 void board_init_f(ulong dummy)
153 struct udevice *pinctrl;
157 /* Example code showing how to enable the debug UART on RK3288 */
158 #include <asm/arch/grf_rk3288.h>
159 /* Enable early UART on the RK3288 */
160 #define GRF_BASE 0xff770000
161 struct rk3288_grf * const grf = (void *)GRF_BASE;
163 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
164 GPIO7C6_MASK << GPIO7C6_SHIFT,
165 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
166 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
168 * Debug UART can be used from here if required:
173 * printascii("string");
176 debug("\nspl:debug uart enabled in %s\n", __func__);
177 ret = spl_early_init();
179 debug("spl_early_init() failed: %d\n", ret);
183 rockchip_timer_init();
186 ret = rockchip_get_clk(&dev);
188 debug("CLK init failed: %d\n", ret);
192 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
194 debug("Pinctrl init failed: %d\n", ret);
198 #if !defined(CONFIG_SPL_OF_PLATDATA)
199 if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
200 ret = phycore_init();
202 debug("Failed to set up phycore power settings: %d\n",
209 #if !defined(CONFIG_SUPPORT_TPL)
210 debug("\nspl:init dram\n");
211 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
213 debug("DRAM init failed: %d\n", ret);
218 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
223 static int setup_led(void)
225 #ifdef CONFIG_SPL_LED
230 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
233 ret = led_get_by_label(led_name, &dev);
235 debug("%s: get=%d\n", __func__, ret);
238 ret = led_set_on(dev, 1);
246 void spl_board_init(void)
248 struct udevice *pinctrl;
254 debug("LED ret=%d\n", ret);
258 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
260 debug("%s: Cannot find pinctrl device\n", __func__);
264 #ifdef CONFIG_SPL_MMC_SUPPORT
265 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
267 debug("%s: Failed to set up SD card\n", __func__);
270 ret = configure_emmc(pinctrl);
272 debug("%s: Failed to set up eMMC\n", __func__);
277 /* Enable debug UART */
278 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
280 debug("%s: Failed to set up console UART\n", __func__);
284 preloader_console_init();
285 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
290 printf("spl_board_init: Error %d\n", ret);
292 /* No way to report error here */
296 #ifdef CONFIG_SPL_OS_BOOT
298 #define PMU_BASE 0xff730000
299 int dram_init_banksize(void)
301 struct rk3288_pmu *const pmu = (void *)PMU_BASE;
302 size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
304 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
305 gd->bd->bi_dram[0].size = size;