arch/arm/mach-rockchip/rk3288/rk3288.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <dm.h>
   7 #include <env.h>
   8 #include <clk.h>
   9 #include <init.h>
  10 #include <malloc.h>
  11 #include <asm/armv7.h>
  12 #include <asm/io.h>
  13 #include <asm/arch-rockchip/bootrom.h>
  14 #include <asm/arch-rockchip/clock.h>
  15 #include <asm/arch-rockchip/cru.h>
  16 #include <asm/arch-rockchip/hardware.h>
  17 #include <asm/arch-rockchip/grf_rk3288.h>
  18 #include <asm/arch-rockchip/pmu_rk3288.h>
  19 #include <asm/arch-rockchip/qos_rk3288.h>
  20 #include <asm/arch-rockchip/sdram.h>
  21 #include <linux/err.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define GRF_BASE        0xff770000
  26
  27 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  28         [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
  29         [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
  30 };
  31
  32 #ifdef CONFIG_SPL_BUILD
  33 static void configure_l2ctlr(void)
  34 {
  35         u32 l2ctlr;
  36
  37         l2ctlr = read_l2ctlr();
  38         l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
  39
  40         /*
  41          * Data RAM write latency: 2 cycles
  42          * Data RAM read latency: 2 cycles
  43          * Data RAM setup latency: 1 cycle
  44          * Tag RAM write latency: 1 cycle
  45          * Tag RAM read latency: 1 cycle
  46          * Tag RAM setup latency: 1 cycle
  47          */
  48         l2ctlr |= (1 << 3 | 1 << 0);
  49         write_l2ctlr(l2ctlr);
  50 }
  51 #endif
  52
  53 int rk3288_qos_init(void)
  54 {
  55         int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
  56         /* set vop qos to higher priority */
  57         writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
  58         writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
  59
  60         if (!fdt_node_check_compatible(gd->fdt_blob, 0,
  61                                        "rockchip,rk3288-tinker")) {
  62                 /* set isp qos to higher priority */
  63                 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
  64                 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
  65                 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
  66         }
  67
  68         return 0;
  69 }
  70
  71 int arch_cpu_init(void)
  72 {
  73 #ifdef CONFIG_SPL_BUILD
  74         configure_l2ctlr();
  75 #else
  76         /* We do some SoC one time setting here. */
  77         struct rk3288_grf * const grf = (void *)GRF_BASE;
  78
  79         /* Use rkpwm by default */
  80         rk_setreg(&grf->soc_con2, 1 << 0);
  81
  82         /*
  83          * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
  84          * cleared
  85          */
  86         rk_clrreg(&grf->soc_con0, 1 << 12);
  87
  88         rk3288_qos_init();
  89 #endif
  90
  91         return 0;
  92 }
  93
  94 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  95 void board_debug_uart_init(void)
  96 {
  97         /* Enable early UART on the RK3288 */
  98         struct rk3288_grf * const grf = (void *)GRF_BASE;
  99
 100         rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
 101                      GPIO7C6_MASK << GPIO7C6_SHIFT,
 102                      GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 103                      GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 104 }
 105 #endif
 106
 107 __weak int rk3288_board_late_init(void)
 108 {
 109         return 0;
 110 }
 111
 112 int rk_board_late_init(void)
 113 {
 114         return rk3288_board_late_init();
 115 }
 116
 117 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
 118                        char * const argv[])
 119 {
 120         static const struct {
 121                 char *name;
 122                 int id;
 123         } clks[] = {
 124                 { "osc", CLK_OSC },
 125                 { "apll", CLK_ARM },
 126                 { "dpll", CLK_DDR },
 127                 { "cpll", CLK_CODEC },
 128                 { "gpll", CLK_GENERAL },
 129 #ifdef CONFIG_ROCKCHIP_RK3036
 130                 { "mpll", CLK_NEW },
 131 #else
 132                 { "npll", CLK_NEW },
 133 #endif
 134         };
 135         int ret, i;
 136         struct udevice *dev;
 137
 138         ret = rockchip_get_clk(&dev);
 139         if (ret) {
 140                 printf("clk-uclass not found\n");
 141                 return 0;
 142         }
 143
 144         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 145                 struct clk clk;
 146                 ulong rate;
 147
 148                 clk.id = clks[i].id;
 149                 ret = clk_request(dev, &clk);
 150                 if (ret < 0)
 151                         continue;
 152
 153                 rate = clk_get_rate(&clk);
 154                 printf("%s: %lu\n", clks[i].name, rate);
 155
 156                 clk_free(&clk);
 157         }
 158
 159         return 0;
 160 }
 161
 162 U_BOOT_CMD(
 163         clock, 2, 1, do_clock,
 164         "display information about clocks",
 165         ""
 166 );