1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
7 #include <asm/arch-rockchip/hardware.h>
8 #include <asm/arch-rockchip/grf_rk3288.h>
9 #include <asm/arch-rockchip/pmu_rk3288.h>
10 #include <asm/arch-rockchip/sdram_common.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 #define GRF_BASE 0xff770000
16 #ifdef CONFIG_SPL_BUILD
17 static void configure_l2ctlr(void)
21 l2ctlr = read_l2ctlr();
22 l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
25 * Data RAM write latency: 2 cycles
26 * Data RAM read latency: 2 cycles
27 * Data RAM setup latency: 1 cycle
28 * Tag RAM write latency: 1 cycle
29 * Tag RAM read latency: 1 cycle
30 * Tag RAM setup latency: 1 cycle
32 l2ctlr |= (1 << 3 | 1 << 0);
37 int arch_cpu_init(void)
39 #ifdef CONFIG_SPL_BUILD
42 /* We do some SoC one time setting here. */
43 struct rk3288_grf * const grf = (void *)GRF_BASE;
45 /* Use rkpwm by default */
46 rk_setreg(&grf->soc_con2, 1 << 0);
52 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
53 void board_debug_uart_init(void)
55 /* Enable early UART on the RK3288 */
56 struct rk3288_grf * const grf = (void *)GRF_BASE;
58 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
59 GPIO7C6_MASK << GPIO7C6_SHIFT,
60 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
61 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
65 #ifdef CONFIG_SPL_OS_BOOT
67 #define PMU_BASE 0xff730000
68 int dram_init_banksize(void)
70 struct rk3288_pmu *const pmu = (void *)PMU_BASE;
71 size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
73 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
74 gd->bd->bi_dram[0].size = size;