1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
10 #include <asm/arch-rockchip/hardware.h>
12 u32 spl_boot_device(void)
14 return BOOT_DEVICE_MMC1;
17 u32 spl_boot_mode(const u32 boot_device)
19 return MMCSD_MODE_RAW;
22 #define TIMER_LOAD_COUNT_L 0x00
23 #define TIMER_LOAD_COUNT_H 0x04
24 #define TIMER_CONTROL_REG 0x10
26 #define TIMER_FMODE BIT(0)
27 #define TIMER_RMODE BIT(1)
29 void rockchip_stimer_init(void)
31 /* If Timer already enabled, don't re-init it */
32 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
37 asm volatile("mcr p15, 0, %0, c14, c0, 0"
38 : : "r"(COUNTER_FREQUENCY));
40 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
41 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
42 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
43 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
47 #define SGRF_DDR_CON0 0x10150000
48 void board_init_f(ulong dummy)
52 ret = spl_early_init();
54 printf("spl_early_init() failed: %d\n", ret);
57 preloader_console_init();
59 /* Init secure timer */
60 rockchip_stimer_init();
61 /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
64 /* Disable the ddr secure region setting to make it non-secure */
65 rk_clrreg(SGRF_DDR_CON0, 0x4000);
68 #ifdef CONFIG_SPL_LOAD_FIT
69 int board_fit_config_name_match(const char *name)
71 /* Just empty function now - can't decide what to choose */
72 debug("%s: %s\n", __func__, name);