arch/arm/mach-rockchip/rk322x/rk322x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5 #include <asm/io.h>
   6 #include <asm/arch-rockchip/bootrom.h>
   7 #include <asm/arch-rockchip/grf_rk322x.h>
   8 #include <asm/arch-rockchip/hardware.h>
   9
  10 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  11         [BROM_BOOTSOURCE_EMMC] = "dwmmc@30020000",
  12         [BROM_BOOTSOURCE_SD] = "dwmmc@30000000",
  13 };
  14
  15 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  16 void board_debug_uart_init(void)
  17 {
  18 #define GRF_BASE        0x11000000
  19         static struct rk322x_grf * const grf = (void *)GRF_BASE;
  20         enum {
  21                 GPIO1B2_SHIFT           = 4,
  22                 GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
  23                 GPIO1B2_GPIO            = 0,
  24                 GPIO1B2_UART1_SIN,
  25                 GPIO1B2_UART21_SIN,
  26
  27                 GPIO1B1_SHIFT           = 2,
  28                 GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
  29                 GPIO1B1_GPIO            = 0,
  30                 GPIO1B1_UART1_SOUT,
  31                 GPIO1B1_UART21_SOUT,
  32         };
  33         enum {
  34                 CON_IOMUX_UART2SEL_SHIFT = 8,
  35                 CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
  36                 CON_IOMUX_UART2SEL_2    = 0,
  37                 CON_IOMUX_UART2SEL_21,
  38         };
  39
  40         /* Enable early UART2 channel 1 on the RK322x */
  41         rk_clrsetreg(&grf->gpio1b_iomux,
  42                      GPIO1B1_MASK | GPIO1B2_MASK,
  43                      GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
  44                      GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
  45         /* Set channel C as UART2 input */
  46         rk_clrsetreg(&grf->con_iomux,
  47                      CON_IOMUX_UART2SEL_MASK,
  48                      CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
  49 }
  50 #endif
  51
  52 int arch_cpu_init(void)
  53 {
  54 #ifdef CONFIG_SPL_BUILD
  55 #define SGRF_BASE       0x10150000
  56         static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE;
  57
  58         /* Disable the ddr secure region setting to make it non-secure */
  59         rk_clrreg(&sgrf->soc_con[0], 0x4000);
  60 #else
  61 #define GRF_BASE        0x11000000
  62         static struct rk322x_grf * const grf = (void *)GRF_BASE;
  63         /*
  64          * The integrated macphy is enabled by default, disable it
  65          * for saving power consuming.
  66          */
  67         rk_clrsetreg(&grf->macphy_con[0],
  68                      MACPHY_CFG_ENABLE_MASK,
  69                      0 << MACPHY_CFG_ENABLE_SHIFT);
  70
  71 #endif
  72         return 0;
  73 }