1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017 Rockchip Electronics Co., Ltd
8 #include <asm/armv8/mmu.h>
10 #include <asm/arch-rockchip/grf_px30.h>
11 #include <asm/arch-rockchip/hardware.h>
12 #include <asm/arch-rockchip/uart.h>
13 #include <asm/arch-rockchip/clock.h>
14 #include <asm/arch-rockchip/cru_px30.h>
15 #include <dt-bindings/clock/px30-cru.h>
17 static struct mm_region px30_mem_map[] = {
22 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
28 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
30 PTE_BLOCK_PXN | PTE_BLOCK_UXN
37 struct mm_region *mem_map = px30_mem_map;
39 #define PMU_PWRDN_CON 0xff000018
40 #define PMUGRF_BASE 0xff010000
41 #define GRF_BASE 0xff140000
42 #define CRU_BASE 0xff2b0000
43 #define VIDEO_PHY_BASE 0xff2e0000
44 #define SERVICE_CORE_ADDR 0xff508000
45 #define DDR_FW_BASE 0xff534000
47 #define FW_DDR_CON 0x40
49 #define QOS_PRIORITY 0x08
51 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
53 /* GRF_GPIO1BH_IOMUX */
56 GPIO1B7_MASK = 0xf << GPIO1B7_SHIFT,
63 GPIO1B6_MASK = 0xf << GPIO1B6_SHIFT,
70 /* GRF_GPIO1CL_IOMUX */
73 GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT,
78 GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT,
83 /* GRF_GPIO1DL_IOMUX */
86 GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT,
92 GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT,
98 /* GRF_GPIO1DH_IOMUX */
101 GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT,
106 GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT,
111 GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT,
116 GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT,
121 /* GRF_GPIO2BH_IOMUX */
124 GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT,
130 GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT,
136 /* GRF_GPIO3AL_IOMUX */
139 GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT,
141 GPIO3A2_UART5_TX = 4,
144 GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT,
146 GPIO3A1_UART5_RX = 4,
149 /* PMUGRF_GPIO0CL_IOMUX */
152 GPIO0C1_MASK = 0x3 << GPIO0C1_SHIFT,
159 GPIO0C0_MASK = 0x3 << GPIO0C0_SHIFT,
166 int arch_cpu_init(void)
168 static struct px30_grf * const grf = (void *)GRF_BASE;
169 u32 __maybe_unused val;
171 #ifdef CONFIG_SPL_BUILD
172 /* We do some SoC one time setting here. */
173 /* Disable the ddr secure region setting to make it non-secure */
174 writel(0x0, DDR_FW_BASE + FW_DDR_CON);
176 /* Set cpu qos priority */
177 writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY);
179 #if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \
180 (CONFIG_DEBUG_UART_BASE != 0xff160000) || \
181 (CONFIG_DEBUG_UART_CHANNEL != 0)
182 /* fix sdmmc pinmux if not using uart2-channel0 as debug uart */
183 rk_clrsetreg(&grf->gpio1dl_iomux,
184 GPIO1D3_MASK | GPIO1D2_MASK,
185 GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT |
186 GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT);
187 rk_clrsetreg(&grf->gpio1dh_iomux,
188 GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK,
189 GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT |
190 GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT |
191 GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT |
192 GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
197 /* Enable PD_VO (default disable at reset) */
198 rk_clrreg(PMU_PWRDN_CON, 1 << 13);
200 /* Disable video phy bandgap by default */
201 writel(0x82, VIDEO_PHY_BASE + 0x0000);
202 writel(0x05, VIDEO_PHY_BASE + 0x03ac);
204 /* Clear the force_jtag */
205 rk_clrreg(&grf->cpu_con[1], 1 << 7);
210 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
211 void board_debug_uart_init(void)
213 #if defined(CONFIG_DEBUG_UART_BASE) && \
214 (CONFIG_DEBUG_UART_BASE == 0xff168000) && \
215 (CONFIG_DEBUG_UART_CHANNEL != 1)
216 static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
218 static struct px30_grf * const grf = (void *)GRF_BASE;
219 static struct px30_cru * const cru = (void *)CRU_BASE;
221 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
222 /* uart_sel_clk default select 24MHz */
223 rk_clrsetreg(&cru->clksel_con[34],
224 UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK,
225 UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0);
226 rk_clrsetreg(&cru->clksel_con[35],
228 UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT);
230 rk_clrsetreg(&grf->gpio1cl_iomux,
231 GPIO1C1_MASK | GPIO1C0_MASK,
232 GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
233 GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
234 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000)
235 /* GRF_IOFUNC_CON0 */
237 CON_IOMUX_UART3SEL_SHIFT = 9,
238 CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
239 CON_IOMUX_UART3SEL_M0 = 0,
240 CON_IOMUX_UART3SEL_M1,
243 /* uart_sel_clk default select 24MHz */
244 rk_clrsetreg(&cru->clksel_con[40],
245 UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK,
246 UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0);
247 rk_clrsetreg(&cru->clksel_con[41],
249 UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT);
251 #if (CONFIG_DEBUG_UART_CHANNEL == 1)
252 rk_clrsetreg(&grf->iofunc_con0,
253 CON_IOMUX_UART3SEL_MASK,
254 CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
256 rk_clrsetreg(&grf->gpio1bh_iomux,
257 GPIO1B7_MASK | GPIO1B6_MASK,
258 GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT |
259 GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
261 rk_clrsetreg(&grf->iofunc_con0,
262 CON_IOMUX_UART3SEL_MASK,
263 CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT);
265 rk_clrsetreg(&pmugrf->gpio0cl_iomux,
266 GPIO0C1_MASK | GPIO0C0_MASK,
267 GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT |
268 GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT);
269 #endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
271 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
272 /* uart_sel_clk default select 24MHz */
273 rk_clrsetreg(&cru->clksel_con[46],
274 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK,
275 UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0);
276 rk_clrsetreg(&cru->clksel_con[47],
278 UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT);
280 rk_clrsetreg(&grf->gpio3al_iomux,
281 GPIO3A2_MASK | GPIO3A1_MASK,
282 GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
283 GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
285 /* GRF_IOFUNC_CON0 */
287 CON_IOMUX_UART2SEL_SHIFT = 10,
288 CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT,
289 CON_IOMUX_UART2SEL_M0 = 0,
290 CON_IOMUX_UART2SEL_M1,
291 CON_IOMUX_UART2SEL_USBPHY,
294 /* uart_sel_clk default select 24MHz */
295 rk_clrsetreg(&cru->clksel_con[37],
296 UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
297 UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
298 rk_clrsetreg(&cru->clksel_con[38],
300 UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
302 #if (CONFIG_DEBUG_UART_CHANNEL == 1)
303 /* Enable early UART2 */
304 rk_clrsetreg(&grf->iofunc_con0,
305 CON_IOMUX_UART2SEL_MASK,
306 CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT);
308 rk_clrsetreg(&grf->gpio2bh_iomux,
309 GPIO2B6_MASK | GPIO2B4_MASK,
310 GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT |
311 GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);
313 rk_clrsetreg(&grf->iofunc_con0,
314 CON_IOMUX_UART2SEL_MASK,
315 CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT);
317 rk_clrsetreg(&grf->gpio1dl_iomux,
318 GPIO1D3_MASK | GPIO1D2_MASK,
319 GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
320 GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
321 #endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
323 #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
325 #endif /* CONFIG_DEBUG_UART_BOARD_INIT */