1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
11 #include <asm/arch-rockchip/boot_mode.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/periph.h>
14 #include <asm/arch-rockchip/misc.h>
15 #include <power/regulator.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 __weak int rk_board_late_init(void)
24 int board_late_init(void)
28 return rk_board_late_init();
35 #ifdef CONFIG_DM_REGULATOR
36 ret = regulators_enable_boot_on(false);
38 debug("%s: Cannot enable boot on regulator\n", __func__);
44 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
45 void enable_caches(void)
47 /* Enable D-cache. I-cache is already enabled in start.S */
52 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
54 #include <usb/dwc2_udc.h>
56 static struct dwc2_plat_otg_data otg_data = {
62 int board_usb_init(int index, enum usb_init_type init)
68 /* find the usb_otg node */
69 node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
70 while (ofnode_valid(node)) {
71 mode = ofnode_read_string(node, "dr_mode");
72 if (mode && strcmp(mode, "otg") == 0) {
77 node = ofnode_by_compatible(node, "snps,dwc2");
80 debug("Not found usb_otg device\n");
83 otg_data.regs_otg = ofnode_get_addr(node);
85 #ifdef CONFIG_ROCKCHIP_RK3288
90 ret = ofnode_read_u32(node, "phys", &phandle);
94 node = ofnode_get_by_phandle(phandle);
95 if (!ofnode_valid(node)) {
96 debug("Not found usb phy device\n");
100 phy_node = ofnode_get_parent(node);
101 if (!ofnode_valid(node)) {
102 debug("Not found usb phy device\n");
106 otg_data.phy_of_node = phy_node;
107 ret = ofnode_read_u32(node, "reg", &offset);
110 otg_data.regs_phy = offset +
111 (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
113 return dwc2_udc_probe(&otg_data);
116 int board_usb_cleanup(int index, enum usb_init_type init)
122 #if CONFIG_IS_ENABLED(FASTBOOT)
123 int fastboot_set_reboot_flag(void)
125 printf("Setting reboot to fastboot flag ...\n");
126 /* Set boot mode to fastboot */
127 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
133 #ifdef CONFIG_MISC_INIT_R
134 __weak int misc_init_r(void)
136 const u32 cpuid_offset = 0x7;
137 const u32 cpuid_length = 0x10;
138 u8 cpuid[cpuid_length];
141 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
145 ret = rockchip_cpuid_set(cpuid, cpuid_length);
149 ret = rockchip_setup_macaddr();