1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
13 #include <asm/arch-rockchip/boot_mode.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/periph.h>
16 #include <asm/arch-rockchip/misc.h>
17 #include <power/regulator.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 __weak int rk_board_late_init(void)
26 int board_late_init(void)
30 return rk_board_late_init();
37 #ifdef CONFIG_DM_REGULATOR
38 ret = regulators_enable_boot_on(false);
40 debug("%s: Cannot enable boot on regulator\n", __func__);
46 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
47 void enable_caches(void)
49 /* Enable D-cache. I-cache is already enabled in start.S */
54 #if defined(CONFIG_USB_GADGET)
57 #if defined(CONFIG_USB_GADGET_DWC2_OTG)
58 #include <usb/dwc2_udc.h>
60 static struct dwc2_plat_otg_data otg_data = {
66 int board_usb_init(int index, enum usb_init_type init)
72 /* find the usb_otg node */
73 node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
74 while (ofnode_valid(node)) {
75 mode = ofnode_read_string(node, "dr_mode");
76 if (mode && strcmp(mode, "otg") == 0) {
81 node = ofnode_by_compatible(node, "snps,dwc2");
84 debug("Not found usb_otg device\n");
87 otg_data.regs_otg = ofnode_get_addr(node);
89 #ifdef CONFIG_ROCKCHIP_RK3288
94 ret = ofnode_read_u32(node, "phys", &phandle);
98 node = ofnode_get_by_phandle(phandle);
99 if (!ofnode_valid(node)) {
100 debug("Not found usb phy device\n");
104 phy_node = ofnode_get_parent(node);
105 if (!ofnode_valid(node)) {
106 debug("Not found usb phy device\n");
110 otg_data.phy_of_node = phy_node;
111 ret = ofnode_read_u32(node, "reg", &offset);
114 otg_data.regs_phy = offset +
115 (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
117 return dwc2_udc_probe(&otg_data);
120 int board_usb_cleanup(int index, enum usb_init_type init)
124 #endif /* CONFIG_USB_GADGET_DWC2_OTG */
126 #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
127 #include <dwc3-uboot.h>
129 static struct dwc3_device dwc3_device_data = {
130 .maximum_speed = USB_SPEED_HIGH,
132 .dr_mode = USB_DR_MODE_PERIPHERAL,
134 .dis_u2_susphy_quirk = 1,
135 .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
138 int usb_gadget_handle_interrupts(void)
140 dwc3_uboot_handle_interrupt(0);
144 int board_usb_init(int index, enum usb_init_type init)
146 return dwc3_uboot_init(&dwc3_device_data);
148 #endif /* CONFIG_USB_DWC3_GADGET */
150 #endif /* CONFIG_USB_GADGET */
152 #if CONFIG_IS_ENABLED(FASTBOOT)
153 int fastboot_set_reboot_flag(void)
155 printf("Setting reboot to fastboot flag ...\n");
156 /* Set boot mode to fastboot */
157 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
163 #ifdef CONFIG_MISC_INIT_R
164 __weak int misc_init_r(void)
166 const u32 cpuid_offset = 0x7;
167 const u32 cpuid_length = 0x10;
168 u8 cpuid[cpuid_length];
171 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
175 ret = rockchip_cpuid_set(cpuid, cpuid_length);
179 ret = rockchip_setup_macaddr();