1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
11 #include <asm/arch-rockchip/boot_mode.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/periph.h>
14 #include <asm/arch-rockchip/misc.h>
15 #include <power/regulator.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 __weak int rk_board_late_init(void)
24 int board_late_init(void)
28 return rk_board_late_init();
35 #ifdef CONFIG_DM_REGULATOR
36 ret = regulators_enable_boot_on(false);
38 debug("%s: Cannot enable boot on regulator\n", __func__);
44 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
45 void enable_caches(void)
47 /* Enable D-cache. I-cache is already enabled in start.S */
52 #if defined(CONFIG_USB_GADGET)
55 #if defined(CONFIG_USB_GADGET_DWC2_OTG)
56 #include <usb/dwc2_udc.h>
58 static struct dwc2_plat_otg_data otg_data = {
64 int board_usb_init(int index, enum usb_init_type init)
70 /* find the usb_otg node */
71 node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
72 while (ofnode_valid(node)) {
73 mode = ofnode_read_string(node, "dr_mode");
74 if (mode && strcmp(mode, "otg") == 0) {
79 node = ofnode_by_compatible(node, "snps,dwc2");
82 debug("Not found usb_otg device\n");
85 otg_data.regs_otg = ofnode_get_addr(node);
87 #ifdef CONFIG_ROCKCHIP_RK3288
92 ret = ofnode_read_u32(node, "phys", &phandle);
96 node = ofnode_get_by_phandle(phandle);
97 if (!ofnode_valid(node)) {
98 debug("Not found usb phy device\n");
102 phy_node = ofnode_get_parent(node);
103 if (!ofnode_valid(node)) {
104 debug("Not found usb phy device\n");
108 otg_data.phy_of_node = phy_node;
109 ret = ofnode_read_u32(node, "reg", &offset);
112 otg_data.regs_phy = offset +
113 (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
115 return dwc2_udc_probe(&otg_data);
118 int board_usb_cleanup(int index, enum usb_init_type init)
122 #endif /* CONFIG_USB_GADGET_DWC2_OTG */
124 #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
125 #include <dwc3-uboot.h>
127 static struct dwc3_device dwc3_device_data = {
128 .maximum_speed = USB_SPEED_HIGH,
130 .dr_mode = USB_DR_MODE_PERIPHERAL,
132 .dis_u2_susphy_quirk = 1,
133 .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
136 int usb_gadget_handle_interrupts(void)
138 dwc3_uboot_handle_interrupt(0);
142 int board_usb_init(int index, enum usb_init_type init)
144 return dwc3_uboot_init(&dwc3_device_data);
146 #endif /* CONFIG_USB_DWC3_GADGET */
148 #endif /* CONFIG_USB_GADGET */
150 #if CONFIG_IS_ENABLED(FASTBOOT)
151 int fastboot_set_reboot_flag(void)
153 printf("Setting reboot to fastboot flag ...\n");
154 /* Set boot mode to fastboot */
155 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
161 #ifdef CONFIG_MISC_INIT_R
162 __weak int misc_init_r(void)
164 const u32 cpuid_offset = 0x7;
165 const u32 cpuid_length = 0x10;
166 u8 cpuid[cpuid_length];
169 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
173 ret = rockchip_cpuid_set(cpuid, cpuid_length);
177 ret = rockchip_setup_macaddr();