1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
12 #include <asm/cache.h>
14 #include <asm/arch-rockchip/boot_mode.h>
15 #include <asm/arch-rockchip/clock.h>
16 #include <asm/arch-rockchip/periph.h>
17 #include <asm/arch-rockchip/misc.h>
18 #include <power/regulator.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 __weak int rk_board_late_init(void)
27 int board_late_init(void)
31 return rk_board_late_init();
38 #ifdef CONFIG_DM_REGULATOR
39 ret = regulators_enable_boot_on(false);
41 debug("%s: Cannot enable boot on regulator\n", __func__);
47 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
48 void enable_caches(void)
50 /* Enable D-cache. I-cache is already enabled in start.S */
55 #if defined(CONFIG_USB_GADGET)
58 #if defined(CONFIG_USB_GADGET_DWC2_OTG)
59 #include <usb/dwc2_udc.h>
61 static struct dwc2_plat_otg_data otg_data = {
67 int board_usb_init(int index, enum usb_init_type init)
73 /* find the usb_otg node */
74 node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
75 while (ofnode_valid(node)) {
76 mode = ofnode_read_string(node, "dr_mode");
77 if (mode && strcmp(mode, "otg") == 0) {
82 node = ofnode_by_compatible(node, "snps,dwc2");
85 debug("Not found usb_otg device\n");
88 otg_data.regs_otg = ofnode_get_addr(node);
90 #ifdef CONFIG_ROCKCHIP_RK3288
95 ret = ofnode_read_u32(node, "phys", &phandle);
99 node = ofnode_get_by_phandle(phandle);
100 if (!ofnode_valid(node)) {
101 debug("Not found usb phy device\n");
105 phy_node = ofnode_get_parent(node);
106 if (!ofnode_valid(node)) {
107 debug("Not found usb phy device\n");
111 otg_data.phy_of_node = phy_node;
112 ret = ofnode_read_u32(node, "reg", &offset);
115 otg_data.regs_phy = offset +
116 (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
118 return dwc2_udc_probe(&otg_data);
121 int board_usb_cleanup(int index, enum usb_init_type init)
125 #endif /* CONFIG_USB_GADGET_DWC2_OTG */
127 #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
128 #include <dwc3-uboot.h>
130 static struct dwc3_device dwc3_device_data = {
131 .maximum_speed = USB_SPEED_HIGH,
133 .dr_mode = USB_DR_MODE_PERIPHERAL,
135 .dis_u2_susphy_quirk = 1,
136 .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
139 int usb_gadget_handle_interrupts(void)
141 dwc3_uboot_handle_interrupt(0);
145 int board_usb_init(int index, enum usb_init_type init)
147 return dwc3_uboot_init(&dwc3_device_data);
149 #endif /* CONFIG_USB_DWC3_GADGET */
151 #endif /* CONFIG_USB_GADGET */
153 #if CONFIG_IS_ENABLED(FASTBOOT)
154 int fastboot_set_reboot_flag(void)
156 printf("Setting reboot to fastboot flag ...\n");
157 /* Set boot mode to fastboot */
158 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
164 #ifdef CONFIG_MISC_INIT_R
165 __weak int misc_init_r(void)
167 const u32 cpuid_offset = 0x7;
168 const u32 cpuid_length = 0x10;
169 u8 cpuid[cpuid_length];
172 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
176 ret = rockchip_cpuid_set(cpuid, cpuid_length);
180 ret = rockchip_setup_macaddr();