1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
13 #include <asm/cache.h>
15 #include <asm/arch-rockchip/boot_mode.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/periph.h>
18 #include <asm/arch-rockchip/misc.h>
19 #include <power/regulator.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 __weak int rk_board_late_init(void)
28 int board_late_init(void)
32 return rk_board_late_init();
39 #ifdef CONFIG_DM_REGULATOR
40 ret = regulators_enable_boot_on(false);
42 debug("%s: Cannot enable boot on regulator\n", __func__);
48 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
49 void enable_caches(void)
51 /* Enable D-cache. I-cache is already enabled in start.S */
56 #if defined(CONFIG_USB_GADGET)
59 #if defined(CONFIG_USB_GADGET_DWC2_OTG)
60 #include <usb/dwc2_udc.h>
62 static struct dwc2_plat_otg_data otg_data = {
68 int board_usb_init(int index, enum usb_init_type init)
74 /* find the usb_otg node */
75 node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
76 while (ofnode_valid(node)) {
77 mode = ofnode_read_string(node, "dr_mode");
78 if (mode && strcmp(mode, "otg") == 0) {
83 node = ofnode_by_compatible(node, "snps,dwc2");
86 debug("Not found usb_otg device\n");
89 otg_data.regs_otg = ofnode_get_addr(node);
91 #ifdef CONFIG_ROCKCHIP_RK3288
96 ret = ofnode_read_u32(node, "phys", &phandle);
100 node = ofnode_get_by_phandle(phandle);
101 if (!ofnode_valid(node)) {
102 debug("Not found usb phy device\n");
106 phy_node = ofnode_get_parent(node);
107 if (!ofnode_valid(node)) {
108 debug("Not found usb phy device\n");
112 otg_data.phy_of_node = phy_node;
113 ret = ofnode_read_u32(node, "reg", &offset);
116 otg_data.regs_phy = offset +
117 (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
119 return dwc2_udc_probe(&otg_data);
122 int board_usb_cleanup(int index, enum usb_init_type init)
126 #endif /* CONFIG_USB_GADGET_DWC2_OTG */
128 #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
129 #include <dwc3-uboot.h>
131 static struct dwc3_device dwc3_device_data = {
132 .maximum_speed = USB_SPEED_HIGH,
134 .dr_mode = USB_DR_MODE_PERIPHERAL,
136 .dis_u2_susphy_quirk = 1,
137 .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
140 int usb_gadget_handle_interrupts(void)
142 dwc3_uboot_handle_interrupt(0);
146 int board_usb_init(int index, enum usb_init_type init)
148 return dwc3_uboot_init(&dwc3_device_data);
150 #endif /* CONFIG_USB_DWC3_GADGET */
152 #endif /* CONFIG_USB_GADGET */
154 #if CONFIG_IS_ENABLED(FASTBOOT)
155 int fastboot_set_reboot_flag(void)
157 printf("Setting reboot to fastboot flag ...\n");
158 /* Set boot mode to fastboot */
159 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
165 #ifdef CONFIG_MISC_INIT_R
166 __weak int misc_init_r(void)
168 const u32 cpuid_offset = 0x7;
169 const u32 cpuid_length = 0x10;
170 u8 cpuid[cpuid_length];
173 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
177 ret = rockchip_cpuid_set(cpuid, cpuid_length);
181 ret = rockchip_setup_macaddr();