4 bool "Support Rockchip RK3036"
8 imply USB_FUNCTION_ROCKUSB
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
16 config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
25 config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
28 select SPL_BOARD_INIT if SPL
35 select SPL_DRIVERS_MISC_SUPPORT
36 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
37 select BOARD_LATE_INIT
38 select ROCKCHIP_BROM_HELPER
40 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
41 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
42 video interfaces, several memory options and video codec support.
43 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
44 UART, SPI, I2C and PWMs.
46 config ROCKCHIP_RK322X
47 bool "Support Rockchip RK3228/RK3229"
57 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
58 select TPL_NEEDS_SEPARATE_STACK if TPL
59 select SPL_DRIVERS_MISC_SUPPORT
60 imply SPL_SERIAL_SUPPORT
61 imply TPL_SERIAL_SUPPORT
62 select ROCKCHIP_BROM_HELPER
63 select TPL_LIBCOMMON_SUPPORT
64 select TPL_LIBGENERIC_SUPPORT
66 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
67 including NEON and GPU, Mali-400 graphics, several DDR3 options
68 and video codec support. Peripherals include Gigabit Ethernet,
69 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
84 config ROCKCHIP_RK3288
85 bool "Support Rockchip RK3288"
87 select SPL_BOARD_INIT if SPL
90 imply USB_FUNCTION_ROCKUSB
93 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
94 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
95 video interfaces supporting HDMI and eDP, several DDR3 options
96 and video codec support. Peripherals include Gigabit Ethernet,
97 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
109 config ROCKCHIP_RK3328
110 bool "Support Rockchip RK3328"
114 imply SPL_SERIAL_SUPPORT
115 imply SPL_SEPARATE_BSS
116 select ENABLE_ARM_SOC_BOOT0_HOOK
117 select DEBUG_UART_BOARD_INIT
120 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
121 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
122 video interfaces supporting HDMI and eDP, several DDR3 options
123 and video codec support. Peripherals include Gigabit Ethernet,
124 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
126 config ROCKCHIP_RK3368
127 bool "Support Rockchip RK3368"
131 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
132 select TPL_NEEDS_SEPARATE_STACK if TPL
133 imply SPL_SEPARATE_BSS
134 imply SPL_SERIAL_SUPPORT
135 imply TPL_SERIAL_SUPPORT
137 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
138 into a big and little cluster with 4 cores each) Cortex-A53 including
139 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
140 (for the little cluster), PowerVR G6110 based graphics, one video
141 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
144 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
145 I2S, UARTs, SPI, I2C and PWMs.
160 config ROCKCHIP_RK3399
161 bool "Support Rockchip RK3399"
167 select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
168 select SPL_BOARD_INIT if SPL
170 select SPL_CLK if SPL
171 select SPL_PINCTRL if SPL
172 select SPL_RAM if SPL
173 select SPL_REGMAP if SPL
174 select SPL_SYSCON if SPL
175 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
176 select TPL_NEEDS_SEPARATE_STACK if TPL
177 select SPL_SEPARATE_BSS
178 select SPL_SERIAL_SUPPORT
179 select SPL_DRIVERS_MISC_SUPPORT
187 select DM_REGULATOR_FIXED
188 select BOARD_LATE_INIT
189 select ROCKCHIP_BROM_HELPER
190 imply TPL_SERIAL_SUPPORT
191 imply TPL_LIBCOMMON_SUPPORT
192 imply TPL_LIBGENERIC_SUPPORT
193 imply TPL_SYS_MALLOC_SIMPLE
195 imply TPL_BOOTROM_SUPPORT
196 imply TPL_DRIVERS_MISC_SUPPORT
203 imply TPL_TINY_MEMSET
205 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
206 and quad-core Cortex-A53.
207 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
208 video interfaces supporting HDMI and eDP, several DDR3 options
209 and video codec support. Peripherals include Gigabit Ethernet,
210 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
215 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
228 config ROCKCHIP_RV1108
229 bool "Support Rockchip RV1108"
232 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
235 config ROCKCHIP_USB_UART
236 bool "Route uart output to usb pins"
238 Rockchip SoCs have the ability to route the signals of the debug
239 uart through the d+ and d- pins of a specific usb phy to enable
240 some form of closed-case debugging. With this option supported
241 SoCs will enable this routing as a debug measure.
243 config SPL_ROCKCHIP_BACK_TO_BROM
244 bool "SPL returns to bootrom"
245 default y if ROCKCHIP_RK3036
246 select ROCKCHIP_BROM_HELPER
249 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
250 SPL will return to the boot rom, which will then load the U-Boot
251 binary to keep going on.
253 config TPL_ROCKCHIP_BACK_TO_BROM
254 bool "TPL returns to bootrom"
256 select ROCKCHIP_BROM_HELPER
259 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
260 SPL will return to the boot rom, which will then load the U-Boot
261 binary to keep going on.
263 config ROCKCHIP_BOOT_MODE_REG
264 hex "Rockchip boot mode flag register address"
265 default 0x200081c8 if ROCKCHIP_RK3036
266 default 0x20004040 if ROCKCHIP_RK3188
267 default 0x110005c8 if ROCKCHIP_RK322X
268 default 0xff730094 if ROCKCHIP_RK3288
269 default 0xff738200 if ROCKCHIP_RK3368
270 default 0xff320300 if ROCKCHIP_RK3399
271 default 0x10300580 if ROCKCHIP_RV1108
274 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
275 according to the value from this register.
277 config ROCKCHIP_SPL_RESERVE_IRAM
278 hex "Size of IRAM reserved in SPL"
281 SPL may need reserve memory for firmware loaded by SPL, whose load
282 address is in IRAM and may overlay with SPL text area if not
285 config ROCKCHIP_BROM_HELPER
288 config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
289 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
290 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
292 Some Rockchip BROM variants (e.g. on the RK3188) load the
293 first stage in segments and enter multiple times. E.g. on
294 the RK3188, the first 1KB of the first stage are loaded
295 first and entered; after returning to the BROM, the
296 remainder of the first stage is loaded, but the BROM
297 re-enters at the same address/to the same code as previously.
299 This enables support code in the BOOT0 hook for the SPL stage
300 to allow multiple entries.
302 config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
303 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
304 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
306 Some Rockchip BROM variants (e.g. on the RK3188) load the
307 first stage in segments and enter multiple times. E.g. on
308 the RK3188, the first 1KB of the first stage are loaded
309 first and entered; after returning to the BROM, the
310 remainder of the first stage is loaded, but the BROM
311 re-enters at the same address/to the same code as previously.
313 This enables support code in the BOOT0 hook for the TPL stage
314 to allow multiple entries.
316 config SPL_MMC_SUPPORT
317 default y if !SPL_ROCKCHIP_BACK_TO_BROM
319 source "arch/arm/mach-rockchip/rk3036/Kconfig"
320 source "arch/arm/mach-rockchip/rk3128/Kconfig"
321 source "arch/arm/mach-rockchip/rk3188/Kconfig"
322 source "arch/arm/mach-rockchip/rk322x/Kconfig"
323 source "arch/arm/mach-rockchip/rk3288/Kconfig"
324 source "arch/arm/mach-rockchip/rk3328/Kconfig"
325 source "arch/arm/mach-rockchip/rk3368/Kconfig"
326 source "arch/arm/mach-rockchip/rk3399/Kconfig"
327 source "arch/arm/mach-rockchip/rv1108/Kconfig"