arch/arm/mach-rmobile/memmap-gen3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Renesas RCar Gen3 memory map tables
   4  *
   5  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/armv8/mmu.h>
  10
  11 #define GEN3_NR_REGIONS 16
  12
  13 static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
  14         {
  15                 .virt = 0x0UL,
  16                 .phys = 0x0UL,
  17                 .size = 0x40000000UL,
  18                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  19                          PTE_BLOCK_NON_SHARE |
  20                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  21         }, {
  22                 .virt = 0x40000000UL,
  23                 .phys = 0x40000000UL,
  24                 .size = 0x03F00000UL,
  25                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  26                          PTE_BLOCK_INNER_SHARE
  27         }, {
  28                 .virt = 0x47E00000UL,
  29                 .phys = 0x47E00000UL,
  30                 .size = 0x78200000UL,
  31                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  32                          PTE_BLOCK_INNER_SHARE
  33         }, {
  34                 .virt = 0xc0000000UL,
  35                 .phys = 0xc0000000UL,
  36                 .size = 0x40000000UL,
  37                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  38                          PTE_BLOCK_NON_SHARE |
  39                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  40         }, {
  41                 .virt = 0x100000000UL,
  42                 .phys = 0x100000000UL,
  43                 .size = 0xf00000000UL,
  44                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  45                          PTE_BLOCK_INNER_SHARE
  46         }, {
  47                 /* List terminator */
  48                 0,
  49         }
  50 };
  51
  52 struct mm_region *mem_map = gen3_mem_map;
  53
  54 DECLARE_GLOBAL_DATA_PTR;
  55
  56 void enable_caches(void)
  57 {
  58         u64 start, size;
  59         int bank, i = 0;
  60
  61         /* Create map for RPC access */
  62         gen3_mem_map[i].virt = 0x0ULL;
  63         gen3_mem_map[i].phys = 0x0ULL;
  64         gen3_mem_map[i].size = 0x40000000ULL;
  65         gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  66                                 PTE_BLOCK_NON_SHARE |
  67                                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
  68         i++;
  69
  70         /* Generate entires for DRAM in 32bit address space */
  71         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
  72                 start = gd->bd->bi_dram[bank].start;
  73                 size = gd->bd->bi_dram[bank].size;
  74
  75                 /* Skip empty DRAM banks */
  76                 if (!size)
  77                         continue;
  78
  79                 /* Skip DRAM above 4 GiB */
  80                 if (start >> 32ULL)
  81                         continue;
  82
  83                 /* Mark memory reserved by ATF as cacheable too. */
  84                 if (start == 0x48000000) {
  85                         start = 0x40000000ULL;
  86                         size += 0x08000000ULL;
  87                 }
  88
  89                 gen3_mem_map[i].virt = start;
  90                 gen3_mem_map[i].phys = start;
  91                 gen3_mem_map[i].size = size;
  92                 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  93                                         PTE_BLOCK_INNER_SHARE;
  94                 i++;
  95         }
  96
  97         /* Create map for register access */
  98         gen3_mem_map[i].virt = 0xc0000000ULL;
  99         gen3_mem_map[i].phys = 0xc0000000ULL;
 100         gen3_mem_map[i].size = 0x40000000ULL;
 101         gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 102                                 PTE_BLOCK_NON_SHARE |
 103                                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 104         i++;
 105
 106         /* Generate entires for DRAM in 64bit address space */
 107         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 108                 start = gd->bd->bi_dram[bank].start;
 109                 size = gd->bd->bi_dram[bank].size;
 110
 111                 /* Skip empty DRAM banks */
 112                 if (!size)
 113                         continue;
 114
 115                 /* Skip DRAM below 4 GiB */
 116                 if (!(start >> 32ULL))
 117                         continue;
 118
 119                 gen3_mem_map[i].virt = start;
 120                 gen3_mem_map[i].phys = start;
 121                 gen3_mem_map[i].size = size;
 122                 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 123                                         PTE_BLOCK_INNER_SHARE;
 124                 i++;
 125         }
 126
 127         /* Zero out the remaining regions. */
 128         for (; i < GEN3_NR_REGIONS; i++) {
 129                 gen3_mem_map[i].virt = 0;
 130                 gen3_mem_map[i].phys = 0;
 131                 gen3_mem_map[i].size = 0;
 132                 gen3_mem_map[i].attrs = 0;
 133         }
 134
 135         icache_enable();
 136         dcache_enable();
 137 }