1 // SPDX-License-Identifier: GPL-2.0+
3 * Renesas RCar Gen3 memory map tables
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
9 #include <asm/armv8/mmu.h>
11 #define GEN3_NR_REGIONS 16
13 static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
18 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
20 PTE_BLOCK_PXN | PTE_BLOCK_UXN
25 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
31 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
39 PTE_BLOCK_PXN | PTE_BLOCK_UXN
41 .virt = 0x100000000UL,
42 .phys = 0x100000000UL,
43 .size = 0xf00000000UL,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
52 struct mm_region *mem_map = gen3_mem_map;
54 DECLARE_GLOBAL_DATA_PTR;
56 void enable_caches(void)
61 /* Create map for RPC access */
62 gen3_mem_map[i].virt = 0x0ULL;
63 gen3_mem_map[i].phys = 0x0ULL;
64 gen3_mem_map[i].size = 0x40000000ULL;
65 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
67 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
70 /* Generate entires for DRAM in 32bit address space */
71 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
72 start = gd->bd->bi_dram[bank].start;
73 size = gd->bd->bi_dram[bank].size;
75 /* Skip empty DRAM banks */
79 /* Skip DRAM above 4 GiB */
83 /* Mark memory reserved by ATF as cacheable too. */
84 if (start == 0x48000000) {
85 start = 0x40000000ULL;
86 size += 0x08000000ULL;
89 gen3_mem_map[i].virt = start;
90 gen3_mem_map[i].phys = start;
91 gen3_mem_map[i].size = size;
92 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
93 PTE_BLOCK_INNER_SHARE;
97 /* Create map for register access */
98 gen3_mem_map[i].virt = 0xc0000000ULL;
99 gen3_mem_map[i].phys = 0xc0000000ULL;
100 gen3_mem_map[i].size = 0x40000000ULL;
101 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
102 PTE_BLOCK_NON_SHARE |
103 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
106 /* Generate entires for DRAM in 64bit address space */
107 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
108 start = gd->bd->bi_dram[bank].start;
109 size = gd->bd->bi_dram[bank].size;
111 /* Skip empty DRAM banks */
115 /* Skip DRAM below 4 GiB */
116 if (!(start >> 32ULL))
119 gen3_mem_map[i].virt = start;
120 gen3_mem_map[i].phys = start;
121 gen3_mem_map[i].size = size;
122 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
123 PTE_BLOCK_INNER_SHARE;
127 /* Zero out the remaining regions. */
128 for (; i < GEN3_NR_REGIONS; i++) {
129 gen3_mem_map[i].virt = 0;
130 gen3_mem_map[i].phys = 0;
131 gen3_mem_map[i].size = 0;
132 gen3_mem_map[i].attrs = 0;