1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2013,2014 Renesas Electronics Corporation
4 * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 #ifndef __EHCI_RMOBILE_H__
8 #define __EHCI_RMOBILE_H__
11 #define OHCI_OFFSET 0x00
12 #define OHCI_SIZE 0x1000
13 #define EHCI_OFFSET 0x1000
14 #define EHCI_SIZE 0x1000
16 #define EHCI_USBCMD (EHCI_OFFSET + 0x0020)
19 #define DIRPD (1 << 8)
20 #define PLL_RST (1 << 2)
21 #define PCICLK_MASK (1 << 1)
22 #define USBH_RST (1 << 0)
25 #define SERREN (1 << 8)
26 #define PERREN (1 << 6)
27 #define MASTEREN (1 << 2)
28 #define MEMEN (1 << 1)
30 /* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */
31 #define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0))
34 #define PCIWIN1_PCICMD ((1 << 3)|(1 << 1))
35 #define AHB_CFG_AHBPCI 0x40000000
36 #define AHB_CFG_HOST 0x80000000
39 #define PCIWIN2_PCICMD ((1 << 2)|(1 << 1))
42 #define USBH_PMEEN (1 << 19)
43 #define USBH_INTBEN (1 << 17)
44 #define USBH_INTAEN (1 << 16)
47 #define SMODE_READY_CTR (1 << 17)
48 #define SMODE_READ_BURST (1 << 16)
49 #define MMODE_HBUSREQ (1 << 7)
50 #define MMODE_BOUNDARY ((1 << 6)|(1 << 5))
51 #define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3))
52 #define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3))
53 #define MMODE_WR_INCR (1 << 2)
54 #define MMODE_BYTE_BURST (1 << 1)
55 #define MMODE_HTRANS (1 << 0)
58 #define PCIBUS_PARK_TIMER 0x00FF0000
59 #define PCIBUS_PARK_TIMER_SET 0x00070000
60 #define PCIBP_MODE (1 << 12)
61 #define PCIREQ7 (1 << 7)
62 #define PCIREQ6 (1 << 6)
63 #define PCIREQ5 (1 << 5)
64 #define PCIREQ4 (1 << 4)
65 #define PCIREQ3 (1 << 3)
66 #define PCIREQ2 (1 << 2)
67 #define PCIREQ1 (1 << 1)
68 #define PCIREQ0 (1 << 0)
70 #define SMSTPCR7 0xE615014C
71 #define SMSTPCR703 (1 << 3)
73 /* Init AHB master and slave functions of the host logic */
74 #define AHB_BUS_CTR_INIT \
75 (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \
76 MMODE_BYTE_BURST | MMODE_HTRANS)
78 #define USBCTR_WIN_SIZE_1GB 0x800
80 /* PCI Configuration Registers */
81 #define PCI_CONF_OHCI_OFFSET 0x10000
82 #define PCI_CONF_EHCI_OFFSET 0x10100
91 /* PCI Configuration Registers for AHB-PCI Bridge Registers */
92 #define PCI_CONF_AHBPCI_OFFSET 0x10000
93 struct ahbconf_pci_bridge {
94 u32 vid_did; /* 0x00 */
98 u32 basead; /* 0x10 */
102 u32 ssvdi_ssid; /* 0x2C */
107 /* AHB-PCI Bridge PCI Communication Registers */
108 #define AHBPCI_OFFSET 0x10800
109 struct ahbcom_pci_bridge {
110 u32 pciahb_win1_ctr; /* 0x00 */
114 u32 ahbpci_win1_ctr; /* 0x10 */
118 u32 pci_int_enable; /* 0x20 */
121 u32 ahb_bus_ctr; /* 0x30 */
124 u32 pci_arbiter_ctr; /* 0x40 */
126 u32 pci_unit_rev; /* 0x48 */
129 struct rmobile_ehci_reg {
130 u32 hciversion; /* hciversion/caplength */
131 u32 hcsparams; /* hcsparams */
132 u32 hccparams; /* hccparams */
133 u32 hcsp_portroute; /* hcsp_portroute */
134 u32 usbcmd; /* usbcmd */
135 u32 usbsts; /* usbsts */
136 u32 usbintr; /* usbintr */
137 u32 frindex; /* frindex */
138 u32 ctrldssegment; /* ctrldssegment */
139 u32 periodiclistbase; /* periodiclistbase */
140 u32 asynclistaddr; /* asynclistaddr */
142 u32 configflag; /* configflag */
143 u32 portsc; /* portsc */
146 #endif /* __EHCI_RMOBILE_H__ */