arch/arm/mach-oxnas/platsmp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   4  * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
   5  * Copyright (C) 2002 ARM Ltd.
   6  * All Rights Reserved
   7  */
   8 #include <linux/io.h>
   9 #include <linux/delay.h>
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12
  13 #include <asm/cacheflush.h>
  14 #include <asm/cp15.h>
  15 #include <asm/smp_plat.h>
  16 #include <asm/smp_scu.h>
  17
  18 extern void ox820_secondary_startup(void);
  19
  20 static void __iomem *cpu_ctrl;
  21 static void __iomem *gic_cpu_ctrl;
  22
  23 #define HOLDINGPEN_CPU_OFFSET           0xc8
  24 #define HOLDINGPEN_LOCATION_OFFSET      0xc4
  25
  26 #define GIC_NCPU_OFFSET(cpu)            (0x100 + (cpu)*0x100)
  27 #define GIC_CPU_CTRL                    0x00
  28 #define GIC_CPU_CTRL_ENABLE             1
  29
  30 int __init ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
  31 {
  32         /*
  33          * Write the address of secondary startup into the
  34          * system-wide flags register. The BootMonitor waits
  35          * until it receives a soft interrupt, and then the
  36          * secondary CPU branches to this address.
  37          */
  38         writel(virt_to_phys(ox820_secondary_startup),
  39                         cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
  40
  41         writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
  42
  43         /*
  44          * Enable GIC cpu interface in CPU Interface Control Register
  45          */
  46         writel(GIC_CPU_CTRL_ENABLE,
  47                 gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
  48
  49         /*
  50          * Send the secondary CPU a soft interrupt, thereby causing
  51          * the boot monitor to read the system wide flags register,
  52          * and branch to the address found there.
  53          */
  54         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  55
  56         return 0;
  57 }
  58
  59 static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
  60 {
  61         struct device_node *np;
  62         void __iomem *scu_base;
  63
  64         np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
  65         scu_base = of_iomap(np, 0);
  66         of_node_put(np);
  67         if (!scu_base)
  68                 return;
  69
  70         /* Remap CPU Interrupt Interface Registers */
  71         np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
  72         gic_cpu_ctrl = of_iomap(np, 1);
  73         of_node_put(np);
  74         if (!gic_cpu_ctrl)
  75                 goto unmap_scu;
  76
  77         np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
  78         cpu_ctrl = of_iomap(np, 0);
  79         of_node_put(np);
  80         if (!cpu_ctrl)
  81                 goto unmap_scu;
  82
  83         scu_enable(scu_base);
  84         flush_cache_all();
  85
  86 unmap_scu:
  87         iounmap(scu_base);
  88 }
  89
  90 static const struct smp_operations ox820_smp_ops __initconst = {
  91         .smp_prepare_cpus       = ox820_smp_prepare_cpus,
  92         .smp_boot_secondary     = ox820_boot_secondary,
  93 };
  94
  95 CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);