1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
5 * Based on original Kirkwood support which is
6 * Copyright (C) Marvell International Ltd. and its affiliates
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
14 #include <linux/delay.h>
16 #define UBOOT_CNTR 0 /* counter to use for uboot timer */
18 /* Timer reload and current value registers */
19 struct orion5x_tmr_val {
20 u32 reload; /* Timer reload reg */
21 u32 val; /* Timer value reg */
25 struct orion5x_tmr_registers {
26 u32 ctrl; /* Timer control reg */
28 struct orion5x_tmr_val tmr[2];
33 struct orion5x_tmr_registers *orion5x_tmr_regs =
34 (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
37 * ARM Timers Registers Map
39 #define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
40 #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
41 #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
44 * ARM Timers Control Register
45 * CPU_TIMERS_CTRL_REG (CTCR)
47 #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
48 #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
49 #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
50 #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
52 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
53 #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
54 #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
55 #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
58 * ARM Timer\Watchdog Reload Register
59 * CNTMR_RELOAD_REG (TRR)
61 #define TRG_ARM_TIMER_REL_OFFS 0
62 #define TRG_ARM_TIMER_REL_MASK 0xffffffff
65 * ARM Timer\Watchdog Register
66 * CNTMR_VAL_REG (TVRG)
68 #define TVR_ARM_TIMER_OFFS 0
69 #define TVR_ARM_TIMER_MASK 0xffffffff
70 #define TVR_ARM_TIMER_MAX 0xffffffff
71 #define TIMER_LOAD_VAL 0xffffffff
73 static inline ulong read_timer(void)
75 return readl(CNTMR_VAL_REG(UBOOT_CNTR))
76 / (CONFIG_SYS_TCLK / 1000);
79 DECLARE_GLOBAL_DATA_PTR;
81 #define timestamp gd->arch.tbl
82 #define lastdec gd->arch.lastinc
84 static ulong get_timer_masked(void)
86 ulong now = read_timer();
90 timestamp += lastdec - now;
92 /* we have an overflow ... */
93 timestamp += lastdec +
94 (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
101 ulong get_timer(ulong base)
103 return get_timer_masked() - base;
106 static inline ulong uboot_cntr_val(void)
108 return readl(CNTMR_VAL_REG(UBOOT_CNTR));
111 void __udelay(unsigned long usec)
116 current = uboot_cntr_val();
117 delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
119 if (current < delayticks) {
120 delayticks -= current;
121 while (uboot_cntr_val() < current)
123 while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
126 while (uboot_cntr_val() > (current - delayticks))
136 unsigned int cntmrctrl;
138 /* load value into timer */
139 writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
140 writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
142 /* enable timer in auto reload mode */
143 cntmrctrl = readl(CNTMR_CTRL_REG);
144 cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
145 cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
146 writel(cntmrctrl, CNTMR_CTRL_REG);
150 void timer_init_r(void)
152 /* init the timestamp and lastdec value */
153 lastdec = read_timer();
158 * This function is derived from PowerPC code (read timebase as long long).
159 * On ARM it just returns the timer value.
161 unsigned long long get_ticks(void)
167 * This function is derived from PowerPC code (timebase clock frequency).
168 * On ARM it returns the number of timer ticks per second.
170 ulong get_tbclk(void)
172 return (ulong)CONFIG_SYS_HZ;