1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
5 * Based on original Kirkwood support which is
6 * Copyright (C) Marvell International Ltd. and its affiliates
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
13 #define UBOOT_CNTR 0 /* counter to use for uboot timer */
15 /* Timer reload and current value registers */
16 struct orion5x_tmr_val {
17 u32 reload; /* Timer reload reg */
18 u32 val; /* Timer value reg */
22 struct orion5x_tmr_registers {
23 u32 ctrl; /* Timer control reg */
25 struct orion5x_tmr_val tmr[2];
30 struct orion5x_tmr_registers *orion5x_tmr_regs =
31 (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
34 * ARM Timers Registers Map
36 #define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
37 #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
38 #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
41 * ARM Timers Control Register
42 * CPU_TIMERS_CTRL_REG (CTCR)
44 #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
45 #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
46 #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
47 #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
49 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
50 #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
51 #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
52 #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
55 * ARM Timer\Watchdog Reload Register
56 * CNTMR_RELOAD_REG (TRR)
58 #define TRG_ARM_TIMER_REL_OFFS 0
59 #define TRG_ARM_TIMER_REL_MASK 0xffffffff
62 * ARM Timer\Watchdog Register
63 * CNTMR_VAL_REG (TVRG)
65 #define TVR_ARM_TIMER_OFFS 0
66 #define TVR_ARM_TIMER_MASK 0xffffffff
67 #define TVR_ARM_TIMER_MAX 0xffffffff
68 #define TIMER_LOAD_VAL 0xffffffff
70 static inline ulong read_timer(void)
72 return readl(CNTMR_VAL_REG(UBOOT_CNTR))
73 / (CONFIG_SYS_TCLK / 1000);
76 DECLARE_GLOBAL_DATA_PTR;
78 #define timestamp gd->arch.tbl
79 #define lastdec gd->arch.lastinc
81 ulong get_timer_masked(void)
83 ulong now = read_timer();
87 timestamp += lastdec - now;
89 /* we have an overflow ... */
90 timestamp += lastdec +
91 (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
98 ulong get_timer(ulong base)
100 return get_timer_masked() - base;
103 static inline ulong uboot_cntr_val(void)
105 return readl(CNTMR_VAL_REG(UBOOT_CNTR));
108 void __udelay(unsigned long usec)
113 current = uboot_cntr_val();
114 delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
116 if (current < delayticks) {
117 delayticks -= current;
118 while (uboot_cntr_val() < current)
120 while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
123 while (uboot_cntr_val() > (current - delayticks))
133 unsigned int cntmrctrl;
135 /* load value into timer */
136 writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
137 writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
139 /* enable timer in auto reload mode */
140 cntmrctrl = readl(CNTMR_CTRL_REG);
141 cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
142 cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
143 writel(cntmrctrl, CNTMR_CTRL_REG);
147 void timer_init_r(void)
149 /* init the timestamp and lastdec value */
150 lastdec = read_timer();
155 * This function is derived from PowerPC code (read timebase as long long).
156 * On ARM it just returns the timer value.
158 unsigned long long get_ticks(void)
164 * This function is derived from PowerPC code (timebase clock frequency).
165 * On ARM it returns the number of timer ticks per second.
167 ulong get_tbclk (void)
169 return (ulong)CONFIG_SYS_HZ;