1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11 #include "asm/arch/orion5x.h"
14 * Configuration values for SDRAM access setup
17 #define SDRAM_CONFIG 0x3148400
18 #define SDRAM_MODE 0x62
19 #define SDRAM_CONTROL 0x4041000
20 #define SDRAM_TIME_CTRL_LOW 0x11602220
21 #define SDRAM_TIME_CTRL_HI 0x40c
22 #define SDRAM_OPEN_PAGE_EN 0x0
23 /* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
24 #define SDRAM_BANK0_SIZE 0x3ff0001
25 #define SDRAM_ADDR_CTRL 0x10
27 #define SDRAM_OP_NOP 0x05
28 #define SDRAM_OP_SETMODE 0x03
30 #define SDRAM_PAD_CTRL_WR_EN 0x80000000
31 #define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
32 #define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
33 #define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
36 * For Guideline MEM-3 - Drive Strength value
39 #define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
40 #define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
43 * For Guideline MEM-4 - DQS Reference Delay Tuning
46 #define MSAR_ARMDDRCLCK_MASK 0x000000f0
47 #define MSAR_ARMDDRCLCK_H_MASK 0x00000100
49 #define MSAR_ARMDDRCLCK_333_167 0x00000000
50 #define MSAR_ARMDDRCLCK_500_167 0x00000030
51 #define MSAR_ARMDDRCLCK_667_167 0x00000060
52 #define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
53 #define MSAR_ARMDDRCLCK_400_200 0x00000010
54 #define MSAR_ARMDDRCLCK_600_200 0x00000050
55 #define MSAR_ARMDDRCLCK_800_200 0x00000070
57 #define FTDLL_DDR1_166MHZ 0x0047F001
59 #define FTDLL_DDR1_200MHZ 0x0044D001
62 * Low-level init happens right after start.S has switched to SVC32,
63 * flushed and disabled caches and disabled MMU. We're still running
64 * from the boot chip select, so the first thing SPL should do is to
65 * set up the RAM to copy U-Boot into.
72 #ifdef CONFIG_SPL_BUILD
74 /* Use 'r2 as the base for internal register accesses */
75 ldr r2, =ORION5X_REGS_PHY_BASE
77 /* move internal registers from the default 0xD0000000
78 * to their intended location, defined by SoC */
83 /* Use R3 as the base for DRAM registers */
86 /*DDR SDRAM Initialization Control */
90 /* Use R3 as the base for PCI registers */
97 /* Use R3 as the base for DRAM registers */
100 /* set all dram windows to 0 */
107 /* 1) Configure SDRAM */
108 ldr r0, =SDRAM_CONFIG
111 /* 2) Set SDRAM Control reg */
112 ldr r0, =SDRAM_CONTROL
115 /* 3) Write SDRAM address control register */
116 ldr r0, =SDRAM_ADDR_CTRL
119 /* 4) Write SDRAM bank 0 size register */
120 ldr r0, =SDRAM_BANK0_SIZE
122 /* keep other banks disabled */
124 /* 5) Write SDRAM open pages control register */
125 ldr r0, =SDRAM_OPEN_PAGE_EN
128 /* 6) Write SDRAM timing Low register */
129 ldr r0, =SDRAM_TIME_CTRL_LOW
132 /* 7) Write SDRAM timing High register */
133 ldr r0, =SDRAM_TIME_CTRL_HI
136 /* 8) Write SDRAM mode register */
137 /* The CPU must not attempt to change the SDRAM Mode register setting */
138 /* prior to DRAM controller completion of the DRAM initialization */
139 /* sequence. To guarantee this restriction, it is recommended that */
140 /* the CPU sets the SDRAM Operation register to NOP command, performs */
141 /* read polling until the register is back in Normal operation value, */
142 /* and then sets SDRAM Mode register to its new value. */
144 /* 8.1 write 'nop' to SDRAM operation */
145 ldr r0, =SDRAM_OP_NOP
148 /* 8.2 poll SDRAM operation until back in 'normal' mode. */
154 /* 8.3 Now its safe to write new value to SDRAM Mode register */
158 /* 8.4 Set new mode */
159 ldr r0, =SDRAM_OP_SETMODE
162 /* 8.5 poll SDRAM operation until back in 'normal' mode. */
168 /* DDR SDRAM Address/Control Pads Calibration */
171 /* Set Bit [31] to make the register writable */
172 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
175 bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
176 bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
177 bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
178 bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
180 /* Get the final N locked value of driving strength [22:17] */
183 mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
184 orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
186 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
190 /* DDR SDRAM Data Pads Calibration */
193 /* Set Bit [31] to make the register writable */
194 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
197 bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
198 bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
199 bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
200 bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
202 /* Get the final N locked value of driving strength [22:17] */
206 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
208 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
213 /* Implement Guideline (GL# MEM-3) Drive Strength Value */
214 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
216 ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
218 /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
220 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
223 /* Correct strength and disable writes again */
224 bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
225 bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
229 /* Enable writes to DDR SDRAM Data Pads Calibration register */
231 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
234 /* Correct strength and disable writes again */
235 bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
236 bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
240 /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
241 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
243 /* Get the "sample on reset" register for the DDR frequancy */
246 ldr r1, =MSAR_ARMDDRCLCK_MASK
249 ldr r0, =FTDLL_DDR1_166MHZ
250 cmp r1, #MSAR_ARMDDRCLCK_333_167
252 cmp r1, #MSAR_ARMDDRCLCK_500_167
254 cmp r1, #MSAR_ARMDDRCLCK_667_167
257 ldr r0, =FTDLL_DDR1_200MHZ
258 cmp r1, #MSAR_ARMDDRCLCK_400_200_1
260 cmp r1, #MSAR_ARMDDRCLCK_400_200
262 cmp r1, #MSAR_ARMDDRCLCK_600_200
264 cmp r1, #MSAR_ARMDDRCLCK_800_200
270 /* Use R3 as the base for DRAM registers */
277 /* enable for 2 GB DDR; detection should find out real amount */
283 #endif /* CONFIG_SPL_BUILD */
285 /* Return to U-Boot via saved link register */