1 // SPDX-License-Identifier: GPL-2.0+
3 * TI SATA platform driver
6 * Texas Instruments, <www.ti.com>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sata.h>
16 #include "pipe3-phy.h"
18 static struct pipe3_dpll_map dpll_map_sata[] = {
19 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
20 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
21 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
22 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
23 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
24 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
28 struct omap_pipe3 sata_phy = {
29 .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
30 /* .power_reg is updated at runtime */
31 .dpll_map = dpll_map_sata,
34 int init_sata(int dev)
39 sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
41 /* Power up the PHY */
42 phy_pipe3_power_on(&sata_phy);
44 /* Enable SATA module, No Idle, No Standby */
45 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
46 writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
48 ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
53 int reset_sata(int dev)
58 /* On OMAP platforms SATA provides the SCSI subsystem */
65 int scsi_bus_reset(struct udevice *dev)
67 ahci_reset((void __iomem *)DWC_AHSATA_BASE);
68 ahci_init((void __iomem *)DWC_AHSATA_BASE);