arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/power/smartreflex.h>
  22
  23 #include <linux/omap-dma.h>
  24
  25 #include "omap_hwmod.h"
  26 #include "omap_hwmod_common_data.h"
  27 #include "cm1_44xx.h"
  28 #include "cm2_44xx.h"
  29 #include "prm44xx.h"
  30 #include "prm-regbits-44xx.h"
  31 #include "wd_timer.h"
  32
  33 /* Base offset for all OMAP4 interrupts external to MPUSS */
  34 #define OMAP44XX_IRQ_GIC_START  32
  35
  36 /* Base offset for all OMAP4 dma requests */
  37 #define OMAP44XX_DMA_REQ_START  1
  38
  39 /*
  40  * IP blocks
  41  */
  42
  43 /*
  44  * 'dmm' class
  45  * instance(s): dmm
  46  */
  47 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  48         .name   = "dmm",
  49 };
  50
  51 /* dmm */
  52 static struct omap_hwmod omap44xx_dmm_hwmod = {
  53         .name           = "dmm",
  54         .class          = &omap44xx_dmm_hwmod_class,
  55         .clkdm_name     = "l3_emif_clkdm",
  56         .prcm = {
  57                 .omap4 = {
  58                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  59                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  60                 },
  61         },
  62 };
  63
  64 /*
  65  * 'l3' class
  66  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  67  */
  68 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  69         .name   = "l3",
  70 };
  71
  72 /* l3_instr */
  73 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  74         .name           = "l3_instr",
  75         .class          = &omap44xx_l3_hwmod_class,
  76         .clkdm_name     = "l3_instr_clkdm",
  77         .prcm = {
  78                 .omap4 = {
  79                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  80                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  81                         .modulemode   = MODULEMODE_HWCTRL,
  82                 },
  83         },
  84 };
  85
  86 /* l3_main_1 */
  87 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  88         .name           = "l3_main_1",
  89         .class          = &omap44xx_l3_hwmod_class,
  90         .clkdm_name     = "l3_1_clkdm",
  91         .prcm = {
  92                 .omap4 = {
  93                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  94                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  95                 },
  96         },
  97 };
  98
  99 /* l3_main_2 */
 100 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 101         .name           = "l3_main_2",
 102         .class          = &omap44xx_l3_hwmod_class,
 103         .clkdm_name     = "l3_2_clkdm",
 104         .prcm = {
 105                 .omap4 = {
 106                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 107                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 108                 },
 109         },
 110 };
 111
 112 /* l3_main_3 */
 113 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 114         .name           = "l3_main_3",
 115         .class          = &omap44xx_l3_hwmod_class,
 116         .clkdm_name     = "l3_instr_clkdm",
 117         .prcm = {
 118                 .omap4 = {
 119                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 120                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 121                         .modulemode   = MODULEMODE_HWCTRL,
 122                 },
 123         },
 124 };
 125
 126 /*
 127  * 'l4' class
 128  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 129  */
 130 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 131         .name   = "l4",
 132 };
 133
 134 /* l4_abe */
 135 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 136         .name           = "l4_abe",
 137         .class          = &omap44xx_l4_hwmod_class,
 138         .clkdm_name     = "abe_clkdm",
 139         .prcm = {
 140                 .omap4 = {
 141                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 142                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 143                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 144                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 145                 },
 146         },
 147 };
 148
 149 /* l4_cfg */
 150 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 151         .name           = "l4_cfg",
 152         .class          = &omap44xx_l4_hwmod_class,
 153         .clkdm_name     = "l4_cfg_clkdm",
 154         .prcm = {
 155                 .omap4 = {
 156                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 157                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 158                 },
 159         },
 160 };
 161
 162 /* l4_per */
 163 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 164         .name           = "l4_per",
 165         .class          = &omap44xx_l4_hwmod_class,
 166         .clkdm_name     = "l4_per_clkdm",
 167         .prcm = {
 168                 .omap4 = {
 169                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 170                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 171                 },
 172         },
 173 };
 174
 175 /* l4_wkup */
 176 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 177         .name           = "l4_wkup",
 178         .class          = &omap44xx_l4_hwmod_class,
 179         .clkdm_name     = "l4_wkup_clkdm",
 180         .prcm = {
 181                 .omap4 = {
 182                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 183                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 184                 },
 185         },
 186 };
 187
 188 /*
 189  * 'mpu_bus' class
 190  * instance(s): mpu_private
 191  */
 192 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 193         .name   = "mpu_bus",
 194 };
 195
 196 /* mpu_private */
 197 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 198         .name           = "mpu_private",
 199         .class          = &omap44xx_mpu_bus_hwmod_class,
 200         .clkdm_name     = "mpuss_clkdm",
 201         .prcm = {
 202                 .omap4 = {
 203                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 204                 },
 205         },
 206 };
 207
 208 /*
 209  * 'ocp_wp_noc' class
 210  * instance(s): ocp_wp_noc
 211  */
 212 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 213         .name   = "ocp_wp_noc",
 214 };
 215
 216 /* ocp_wp_noc */
 217 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 218         .name           = "ocp_wp_noc",
 219         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 220         .clkdm_name     = "l3_instr_clkdm",
 221         .prcm = {
 222                 .omap4 = {
 223                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 224                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 225                         .modulemode   = MODULEMODE_HWCTRL,
 226                 },
 227         },
 228 };
 229
 230 /*
 231  * Modules omap_hwmod structures
 232  *
 233  * The following IPs are excluded for the moment because:
 234  * - They do not need an explicit SW control using omap_hwmod API.
 235  * - They still need to be validated with the driver
 236  *   properly adapted to omap_hwmod / omap_device
 237  *
 238  * usim
 239  */
 240
 241 /*
 242  * 'aess' class
 243  * audio engine sub system
 244  */
 245
 246 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 247         .rev_offs       = 0x0000,
 248         .sysc_offs      = 0x0010,
 249         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 250         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 251                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 252                            MSTANDBY_SMART_WKUP),
 253         .sysc_fields    = &omap_hwmod_sysc_type2,
 254 };
 255
 256 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 257         .name   = "aess",
 258         .sysc   = &omap44xx_aess_sysc,
 259         .enable_preprogram = omap_hwmod_aess_preprogram,
 260 };
 261
 262 /* aess */
 263 static struct omap_hwmod omap44xx_aess_hwmod = {
 264         .name           = "aess",
 265         .class          = &omap44xx_aess_hwmod_class,
 266         .clkdm_name     = "abe_clkdm",
 267         .main_clk       = "aess_fclk",
 268         .prcm = {
 269                 .omap4 = {
 270                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 271                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 272                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 273                         .modulemode   = MODULEMODE_SWCTRL,
 274                 },
 275         },
 276 };
 277
 278 /*
 279  * 'c2c' class
 280  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 281  * soc
 282  */
 283
 284 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 285         .name   = "c2c",
 286 };
 287
 288 /* c2c */
 289 static struct omap_hwmod omap44xx_c2c_hwmod = {
 290         .name           = "c2c",
 291         .class          = &omap44xx_c2c_hwmod_class,
 292         .clkdm_name     = "d2d_clkdm",
 293         .prcm = {
 294                 .omap4 = {
 295                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 296                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 297                 },
 298         },
 299 };
 300
 301 /*
 302  * 'counter' class
 303  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 304  */
 305
 306 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 307         .rev_offs       = 0x0000,
 308         .sysc_offs      = 0x0004,
 309         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 310         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 311         .sysc_fields    = &omap_hwmod_sysc_type1,
 312 };
 313
 314 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 315         .name   = "counter",
 316         .sysc   = &omap44xx_counter_sysc,
 317 };
 318
 319 /* counter_32k */
 320 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 321         .name           = "counter_32k",
 322         .class          = &omap44xx_counter_hwmod_class,
 323         .clkdm_name     = "l4_wkup_clkdm",
 324         .flags          = HWMOD_SWSUP_SIDLE,
 325         .main_clk       = "sys_32k_ck",
 326         .prcm = {
 327                 .omap4 = {
 328                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 329                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 330                 },
 331         },
 332 };
 333
 334 /*
 335  * 'ctrl_module' class
 336  * attila core control module + core pad control module + wkup pad control
 337  * module + attila wkup control module
 338  */
 339
 340 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 341         .rev_offs       = 0x0000,
 342         .sysc_offs      = 0x0010,
 343         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 344         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 345                            SIDLE_SMART_WKUP),
 346         .sysc_fields    = &omap_hwmod_sysc_type2,
 347 };
 348
 349 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 350         .name   = "ctrl_module",
 351         .sysc   = &omap44xx_ctrl_module_sysc,
 352 };
 353
 354 /* ctrl_module_core */
 355 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 356         .name           = "ctrl_module_core",
 357         .class          = &omap44xx_ctrl_module_hwmod_class,
 358         .clkdm_name     = "l4_cfg_clkdm",
 359         .prcm = {
 360                 .omap4 = {
 361                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 362                 },
 363         },
 364 };
 365
 366 /* ctrl_module_pad_core */
 367 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 368         .name           = "ctrl_module_pad_core",
 369         .class          = &omap44xx_ctrl_module_hwmod_class,
 370         .clkdm_name     = "l4_cfg_clkdm",
 371         .prcm = {
 372                 .omap4 = {
 373                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 374                 },
 375         },
 376 };
 377
 378 /* ctrl_module_wkup */
 379 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 380         .name           = "ctrl_module_wkup",
 381         .class          = &omap44xx_ctrl_module_hwmod_class,
 382         .clkdm_name     = "l4_wkup_clkdm",
 383         .prcm = {
 384                 .omap4 = {
 385                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 386                 },
 387         },
 388 };
 389
 390 /* ctrl_module_pad_wkup */
 391 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 392         .name           = "ctrl_module_pad_wkup",
 393         .class          = &omap44xx_ctrl_module_hwmod_class,
 394         .clkdm_name     = "l4_wkup_clkdm",
 395         .prcm = {
 396                 .omap4 = {
 397                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 398                 },
 399         },
 400 };
 401
 402 /*
 403  * 'debugss' class
 404  * debug and emulation sub system
 405  */
 406
 407 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 408         .name   = "debugss",
 409 };
 410
 411 /* debugss */
 412 static struct omap_hwmod omap44xx_debugss_hwmod = {
 413         .name           = "debugss",
 414         .class          = &omap44xx_debugss_hwmod_class,
 415         .clkdm_name     = "emu_sys_clkdm",
 416         .main_clk       = "trace_clk_div_ck",
 417         .prcm = {
 418                 .omap4 = {
 419                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 420                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 421                 },
 422         },
 423 };
 424
 425 /*
 426  * 'dma' class
 427  * dma controller for data exchange between memory to memory (i.e. internal or
 428  * external memory) and gp peripherals to memory or memory to gp peripherals
 429  */
 430
 431 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 432         .rev_offs       = 0x0000,
 433         .sysc_offs      = 0x002c,
 434         .syss_offs      = 0x0028,
 435         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 436                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 437                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 438                            SYSS_HAS_RESET_STATUS),
 439         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 440                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 441         .sysc_fields    = &omap_hwmod_sysc_type1,
 442 };
 443
 444 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 445         .name   = "dma",
 446         .sysc   = &omap44xx_dma_sysc,
 447 };
 448
 449 /* dma dev_attr */
 450 static struct omap_dma_dev_attr dma_dev_attr = {
 451         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 452                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 453         .lch_count      = 32,
 454 };
 455
 456 /* dma_system */
 457 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 458         .name           = "dma_system",
 459         .class          = &omap44xx_dma_hwmod_class,
 460         .clkdm_name     = "l3_dma_clkdm",
 461         .main_clk       = "l3_div_ck",
 462         .prcm = {
 463                 .omap4 = {
 464                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 465                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 466                 },
 467         },
 468         .dev_attr       = &dma_dev_attr,
 469 };
 470
 471 /*
 472  * 'dmic' class
 473  * digital microphone controller
 474  */
 475
 476 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 477         .rev_offs       = 0x0000,
 478         .sysc_offs      = 0x0010,
 479         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 480                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 481         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 482                            SIDLE_SMART_WKUP),
 483         .sysc_fields    = &omap_hwmod_sysc_type2,
 484 };
 485
 486 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 487         .name   = "dmic",
 488         .sysc   = &omap44xx_dmic_sysc,
 489 };
 490
 491 /* dmic */
 492 static struct omap_hwmod omap44xx_dmic_hwmod = {
 493         .name           = "dmic",
 494         .class          = &omap44xx_dmic_hwmod_class,
 495         .clkdm_name     = "abe_clkdm",
 496         .main_clk       = "func_dmic_abe_gfclk",
 497         .prcm = {
 498                 .omap4 = {
 499                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 500                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 501                         .modulemode   = MODULEMODE_SWCTRL,
 502                 },
 503         },
 504 };
 505
 506 /*
 507  * 'dsp' class
 508  * dsp sub-system
 509  */
 510
 511 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 512         .name   = "dsp",
 513 };
 514
 515 /* dsp */
 516 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 517         { .name = "dsp", .rst_shift = 0 },
 518 };
 519
 520 static struct omap_hwmod omap44xx_dsp_hwmod = {
 521         .name           = "dsp",
 522         .class          = &omap44xx_dsp_hwmod_class,
 523         .clkdm_name     = "tesla_clkdm",
 524         .rst_lines      = omap44xx_dsp_resets,
 525         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 526         .main_clk       = "dpll_iva_m4x2_ck",
 527         .prcm = {
 528                 .omap4 = {
 529                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 530                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 531                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 532                         .modulemode   = MODULEMODE_HWCTRL,
 533                 },
 534         },
 535 };
 536
 537 /*
 538  * 'dss' class
 539  * display sub-system
 540  */
 541
 542 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 543         .rev_offs       = 0x0000,
 544         .syss_offs      = 0x0014,
 545         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 546 };
 547
 548 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 549         .name   = "dss",
 550         .sysc   = &omap44xx_dss_sysc,
 551         .reset  = omap_dss_reset,
 552 };
 553
 554 /* dss */
 555 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 556         { .role = "sys_clk", .clk = "dss_sys_clk" },
 557         { .role = "tv_clk", .clk = "dss_tv_clk" },
 558         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 559 };
 560
 561 static struct omap_hwmod omap44xx_dss_hwmod = {
 562         .name           = "dss_core",
 563         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 564         .class          = &omap44xx_dss_hwmod_class,
 565         .clkdm_name     = "l3_dss_clkdm",
 566         .main_clk       = "dss_dss_clk",
 567         .prcm = {
 568                 .omap4 = {
 569                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 570                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 571                         .modulemode   = MODULEMODE_SWCTRL,
 572                 },
 573         },
 574         .opt_clks       = dss_opt_clks,
 575         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 576 };
 577
 578 /*
 579  * 'dispc' class
 580  * display controller
 581  */
 582
 583 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 584         .rev_offs       = 0x0000,
 585         .sysc_offs      = 0x0010,
 586         .syss_offs      = 0x0014,
 587         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 588                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 589                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 590                            SYSS_HAS_RESET_STATUS),
 591         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 592                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 593         .sysc_fields    = &omap_hwmod_sysc_type1,
 594 };
 595
 596 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 597         .name   = "dispc",
 598         .sysc   = &omap44xx_dispc_sysc,
 599 };
 600
 601 /* dss_dispc */
 602 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 603         .manager_count          = 3,
 604         .has_framedonetv_irq    = 1
 605 };
 606
 607 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 608         .name           = "dss_dispc",
 609         .class          = &omap44xx_dispc_hwmod_class,
 610         .clkdm_name     = "l3_dss_clkdm",
 611         .main_clk       = "dss_dss_clk",
 612         .prcm = {
 613                 .omap4 = {
 614                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 615                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 616                 },
 617         },
 618         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 619         .parent_hwmod   = &omap44xx_dss_hwmod,
 620 };
 621
 622 /*
 623  * 'dsi' class
 624  * display serial interface controller
 625  */
 626
 627 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 628         .rev_offs       = 0x0000,
 629         .sysc_offs      = 0x0010,
 630         .syss_offs      = 0x0014,
 631         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 632                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 633                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 634         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 635         .sysc_fields    = &omap_hwmod_sysc_type1,
 636 };
 637
 638 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 639         .name   = "dsi",
 640         .sysc   = &omap44xx_dsi_sysc,
 641 };
 642
 643 /* dss_dsi1 */
 644 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 645         { .role = "sys_clk", .clk = "dss_sys_clk" },
 646 };
 647
 648 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 649         .name           = "dss_dsi1",
 650         .class          = &omap44xx_dsi_hwmod_class,
 651         .clkdm_name     = "l3_dss_clkdm",
 652         .main_clk       = "dss_dss_clk",
 653         .prcm = {
 654                 .omap4 = {
 655                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 656                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 657                 },
 658         },
 659         .opt_clks       = dss_dsi1_opt_clks,
 660         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 661         .parent_hwmod   = &omap44xx_dss_hwmod,
 662 };
 663
 664 /* dss_dsi2 */
 665 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 666         { .role = "sys_clk", .clk = "dss_sys_clk" },
 667 };
 668
 669 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 670         .name           = "dss_dsi2",
 671         .class          = &omap44xx_dsi_hwmod_class,
 672         .clkdm_name     = "l3_dss_clkdm",
 673         .main_clk       = "dss_dss_clk",
 674         .prcm = {
 675                 .omap4 = {
 676                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 677                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 678                 },
 679         },
 680         .opt_clks       = dss_dsi2_opt_clks,
 681         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 682         .parent_hwmod   = &omap44xx_dss_hwmod,
 683 };
 684
 685 /*
 686  * 'hdmi' class
 687  * hdmi controller
 688  */
 689
 690 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 691         .rev_offs       = 0x0000,
 692         .sysc_offs      = 0x0010,
 693         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 694                            SYSC_HAS_SOFTRESET),
 695         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 696                            SIDLE_SMART_WKUP),
 697         .sysc_fields    = &omap_hwmod_sysc_type2,
 698 };
 699
 700 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 701         .name   = "hdmi",
 702         .sysc   = &omap44xx_hdmi_sysc,
 703 };
 704
 705 /* dss_hdmi */
 706 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 707         { .role = "sys_clk", .clk = "dss_sys_clk" },
 708         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 709 };
 710
 711 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 712         .name           = "dss_hdmi",
 713         .class          = &omap44xx_hdmi_hwmod_class,
 714         .clkdm_name     = "l3_dss_clkdm",
 715         /*
 716          * HDMI audio requires to use no-idle mode. Hence,
 717          * set idle mode by software.
 718          */
 719         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
 720         .main_clk       = "dss_48mhz_clk",
 721         .prcm = {
 722                 .omap4 = {
 723                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 724                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 725                 },
 726         },
 727         .opt_clks       = dss_hdmi_opt_clks,
 728         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 729         .parent_hwmod   = &omap44xx_dss_hwmod,
 730 };
 731
 732 /*
 733  * 'rfbi' class
 734  * remote frame buffer interface
 735  */
 736
 737 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 738         .rev_offs       = 0x0000,
 739         .sysc_offs      = 0x0010,
 740         .syss_offs      = 0x0014,
 741         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 742                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 743         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 744         .sysc_fields    = &omap_hwmod_sysc_type1,
 745 };
 746
 747 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 748         .name   = "rfbi",
 749         .sysc   = &omap44xx_rfbi_sysc,
 750 };
 751
 752 /* dss_rfbi */
 753 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 754         { .role = "ick", .clk = "l3_div_ck" },
 755 };
 756
 757 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 758         .name           = "dss_rfbi",
 759         .class          = &omap44xx_rfbi_hwmod_class,
 760         .clkdm_name     = "l3_dss_clkdm",
 761         .main_clk       = "dss_dss_clk",
 762         .prcm = {
 763                 .omap4 = {
 764                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 765                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 766                 },
 767         },
 768         .opt_clks       = dss_rfbi_opt_clks,
 769         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 770         .parent_hwmod   = &omap44xx_dss_hwmod,
 771 };
 772
 773 /*
 774  * 'venc' class
 775  * video encoder
 776  */
 777
 778 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 779         .name   = "venc",
 780 };
 781
 782 /* dss_venc */
 783 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 784         { .role = "tv_clk", .clk = "dss_tv_clk" },
 785 };
 786
 787 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 788         .name           = "dss_venc",
 789         .class          = &omap44xx_venc_hwmod_class,
 790         .clkdm_name     = "l3_dss_clkdm",
 791         .main_clk       = "dss_tv_clk",
 792         .flags          = HWMOD_OPT_CLKS_NEEDED,
 793         .prcm = {
 794                 .omap4 = {
 795                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 796                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 797                 },
 798         },
 799         .parent_hwmod   = &omap44xx_dss_hwmod,
 800         .opt_clks       = dss_venc_opt_clks,
 801         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 802 };
 803
 804 /* sha0 HIB2 (the 'P' (public) device) */
 805 static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
 806         .rev_offs       = 0x100,
 807         .sysc_offs      = 0x110,
 808         .syss_offs      = 0x114,
 809         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 810 };
 811
 812 static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
 813         .name           = "sham",
 814         .sysc           = &omap44xx_sha0_sysc,
 815 };
 816
 817 struct omap_hwmod omap44xx_sha0_hwmod = {
 818         .name           = "sham",
 819         .class          = &omap44xx_sha0_hwmod_class,
 820         .clkdm_name     = "l4_secure_clkdm",
 821         .main_clk       = "l3_div_ck",
 822         .prcm           = {
 823                 .omap4 = {
 824                         .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 825                         .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 826                         .modulemode   = MODULEMODE_SWCTRL,
 827                 },
 828         },
 829 };
 830
 831 /*
 832  * 'elm' class
 833  * bch error location module
 834  */
 835
 836 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 837         .rev_offs       = 0x0000,
 838         .sysc_offs      = 0x0010,
 839         .syss_offs      = 0x0014,
 840         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 841                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 842                            SYSS_HAS_RESET_STATUS),
 843         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 844         .sysc_fields    = &omap_hwmod_sysc_type1,
 845 };
 846
 847 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 848         .name   = "elm",
 849         .sysc   = &omap44xx_elm_sysc,
 850 };
 851
 852 /* elm */
 853 static struct omap_hwmod omap44xx_elm_hwmod = {
 854         .name           = "elm",
 855         .class          = &omap44xx_elm_hwmod_class,
 856         .clkdm_name     = "l4_per_clkdm",
 857         .prcm = {
 858                 .omap4 = {
 859                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 860                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 861                 },
 862         },
 863 };
 864
 865 /*
 866  * 'emif' class
 867  * external memory interface no1
 868  */
 869
 870 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 871         .rev_offs       = 0x0000,
 872 };
 873
 874 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 875         .name   = "emif",
 876         .sysc   = &omap44xx_emif_sysc,
 877 };
 878
 879 /* emif1 */
 880 static struct omap_hwmod omap44xx_emif1_hwmod = {
 881         .name           = "emif1",
 882         .class          = &omap44xx_emif_hwmod_class,
 883         .clkdm_name     = "l3_emif_clkdm",
 884         .flags          = HWMOD_INIT_NO_IDLE,
 885         .main_clk       = "ddrphy_ck",
 886         .prcm = {
 887                 .omap4 = {
 888                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 889                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 890                         .modulemode   = MODULEMODE_HWCTRL,
 891                 },
 892         },
 893 };
 894
 895 /* emif2 */
 896 static struct omap_hwmod omap44xx_emif2_hwmod = {
 897         .name           = "emif2",
 898         .class          = &omap44xx_emif_hwmod_class,
 899         .clkdm_name     = "l3_emif_clkdm",
 900         .flags          = HWMOD_INIT_NO_IDLE,
 901         .main_clk       = "ddrphy_ck",
 902         .prcm = {
 903                 .omap4 = {
 904                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 905                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 906                         .modulemode   = MODULEMODE_HWCTRL,
 907                 },
 908         },
 909 };
 910
 911 /*
 912     Crypto modules AES0/1 belong to:
 913         PD_L4_PER power domain
 914         CD_L4_SEC clock domain
 915         On the L3, the AES modules are mapped to
 916         L3_CLK2: Peripherals and multimedia sub clock domain
 917 */
 918 static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
 919         .rev_offs       = 0x80,
 920         .sysc_offs      = 0x84,
 921         .syss_offs      = 0x88,
 922         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 923 };
 924
 925 static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
 926         .name           = "aes",
 927         .sysc           = &omap44xx_aes_sysc,
 928 };
 929
 930 static struct omap_hwmod omap44xx_aes1_hwmod = {
 931         .name           = "aes1",
 932         .class          = &omap44xx_aes_hwmod_class,
 933         .clkdm_name     = "l4_secure_clkdm",
 934         .main_clk       = "l3_div_ck",
 935         .prcm           = {
 936                 .omap4  = {
 937                         .context_offs   = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
 938                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 939                         .modulemode     = MODULEMODE_SWCTRL,
 940                 },
 941         },
 942 };
 943
 944 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
 945         .master         = &omap44xx_l4_per_hwmod,
 946         .slave          = &omap44xx_aes1_hwmod,
 947         .clk            = "l3_div_ck",
 948         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 949 };
 950
 951 static struct omap_hwmod omap44xx_aes2_hwmod = {
 952         .name           = "aes2",
 953         .class          = &omap44xx_aes_hwmod_class,
 954         .clkdm_name     = "l4_secure_clkdm",
 955         .main_clk       = "l3_div_ck",
 956         .prcm           = {
 957                 .omap4  = {
 958                         .context_offs   = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
 959                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 960                         .modulemode     = MODULEMODE_SWCTRL,
 961                 },
 962         },
 963 };
 964
 965 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
 966         .master         = &omap44xx_l4_per_hwmod,
 967         .slave          = &omap44xx_aes2_hwmod,
 968         .clk            = "l3_div_ck",
 969         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 970 };
 971
 972 /*
 973  * 'des' class for DES3DES module
 974  */
 975 static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
 976         .rev_offs       = 0x30,
 977         .sysc_offs      = 0x34,
 978         .syss_offs      = 0x38,
 979         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 980 };
 981
 982 static struct omap_hwmod_class omap44xx_des_hwmod_class = {
 983         .name           = "des",
 984         .sysc           = &omap44xx_des_sysc,
 985 };
 986
 987 static struct omap_hwmod omap44xx_des_hwmod = {
 988         .name           = "des",
 989         .class          = &omap44xx_des_hwmod_class,
 990         .clkdm_name     = "l4_secure_clkdm",
 991         .main_clk       = "l3_div_ck",
 992         .prcm           = {
 993                 .omap4  = {
 994                         .context_offs   = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
 995                         .clkctrl_offs   = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
 996                         .modulemode     = MODULEMODE_SWCTRL,
 997                 },
 998         },
 999 };
1000
1001 struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
1002         .master         = &omap44xx_l3_main_2_hwmod,
1003         .slave          = &omap44xx_des_hwmod,
1004         .clk            = "l3_div_ck",
1005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1006 };
1007
1008 /*
1009  * 'fdif' class
1010  * face detection hw accelerator module
1011  */
1012
1013 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1014         .rev_offs       = 0x0000,
1015         .sysc_offs      = 0x0010,
1016         /*
1017          * FDIF needs 100 OCP clk cycles delay after a softreset before
1018          * accessing sysconfig again.
1019          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1020          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1021          *
1022          * TODO: Indicate errata when available.
1023          */
1024         .srst_udelay    = 2,
1025         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1026                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1027         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1028                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1029         .sysc_fields    = &omap_hwmod_sysc_type2,
1030 };
1031
1032 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1033         .name   = "fdif",
1034         .sysc   = &omap44xx_fdif_sysc,
1035 };
1036
1037 /* fdif */
1038 static struct omap_hwmod omap44xx_fdif_hwmod = {
1039         .name           = "fdif",
1040         .class          = &omap44xx_fdif_hwmod_class,
1041         .clkdm_name     = "iss_clkdm",
1042         .main_clk       = "fdif_fck",
1043         .prcm = {
1044                 .omap4 = {
1045                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1046                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1047                         .modulemode   = MODULEMODE_SWCTRL,
1048                 },
1049         },
1050 };
1051
1052 /*
1053  * 'gpmc' class
1054  * general purpose memory controller
1055  */
1056
1057 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1058         .rev_offs       = 0x0000,
1059         .sysc_offs      = 0x0010,
1060         .syss_offs      = 0x0014,
1061         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1062                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1063         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1064         .sysc_fields    = &omap_hwmod_sysc_type1,
1065 };
1066
1067 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1068         .name   = "gpmc",
1069         .sysc   = &omap44xx_gpmc_sysc,
1070 };
1071
1072 /* gpmc */
1073 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1074         .name           = "gpmc",
1075         .class          = &omap44xx_gpmc_hwmod_class,
1076         .clkdm_name     = "l3_2_clkdm",
1077         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1078         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1079         .prcm = {
1080                 .omap4 = {
1081                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1082                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1083                         .modulemode   = MODULEMODE_HWCTRL,
1084                 },
1085         },
1086 };
1087
1088 /*
1089  * 'gpu' class
1090  * 2d/3d graphics accelerator
1091  */
1092
1093 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1094         .rev_offs       = 0x1fc00,
1095         .sysc_offs      = 0x1fc10,
1096         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1097         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1098                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1099                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1100         .sysc_fields    = &omap_hwmod_sysc_type2,
1101 };
1102
1103 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1104         .name   = "gpu",
1105         .sysc   = &omap44xx_gpu_sysc,
1106 };
1107
1108 /* gpu */
1109 static struct omap_hwmod omap44xx_gpu_hwmod = {
1110         .name           = "gpu",
1111         .class          = &omap44xx_gpu_hwmod_class,
1112         .clkdm_name     = "l3_gfx_clkdm",
1113         .main_clk       = "sgx_clk_mux",
1114         .prcm = {
1115                 .omap4 = {
1116                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1117                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1118                         .modulemode   = MODULEMODE_SWCTRL,
1119                 },
1120         },
1121 };
1122
1123 /*
1124  * 'hdq1w' class
1125  * hdq / 1-wire serial interface controller
1126  */
1127
1128 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1129         .rev_offs       = 0x0000,
1130         .sysc_offs      = 0x0014,
1131         .syss_offs      = 0x0018,
1132         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1133                            SYSS_HAS_RESET_STATUS),
1134         .sysc_fields    = &omap_hwmod_sysc_type1,
1135 };
1136
1137 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1138         .name   = "hdq1w",
1139         .sysc   = &omap44xx_hdq1w_sysc,
1140 };
1141
1142 /* hdq1w */
1143 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1144         .name           = "hdq1w",
1145         .class          = &omap44xx_hdq1w_hwmod_class,
1146         .clkdm_name     = "l4_per_clkdm",
1147         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1148         .main_clk       = "func_12m_fclk",
1149         .prcm = {
1150                 .omap4 = {
1151                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1152                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1153                         .modulemode   = MODULEMODE_SWCTRL,
1154                 },
1155         },
1156 };
1157
1158 /*
1159  * 'hsi' class
1160  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1161  * serial if)
1162  */
1163
1164 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1165         .rev_offs       = 0x0000,
1166         .sysc_offs      = 0x0010,
1167         .syss_offs      = 0x0014,
1168         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1169                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1170                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1171         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1172                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1173                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1174         .sysc_fields    = &omap_hwmod_sysc_type1,
1175 };
1176
1177 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1178         .name   = "hsi",
1179         .sysc   = &omap44xx_hsi_sysc,
1180 };
1181
1182 /* hsi */
1183 static struct omap_hwmod omap44xx_hsi_hwmod = {
1184         .name           = "hsi",
1185         .class          = &omap44xx_hsi_hwmod_class,
1186         .clkdm_name     = "l3_init_clkdm",
1187         .main_clk       = "hsi_fck",
1188         .prcm = {
1189                 .omap4 = {
1190                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1191                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1192                         .modulemode   = MODULEMODE_HWCTRL,
1193                 },
1194         },
1195 };
1196
1197 /*
1198  * 'ipu' class
1199  * imaging processor unit
1200  */
1201
1202 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1203         .name   = "ipu",
1204 };
1205
1206 /* ipu */
1207 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1208         { .name = "cpu0", .rst_shift = 0 },
1209         { .name = "cpu1", .rst_shift = 1 },
1210 };
1211
1212 static struct omap_hwmod omap44xx_ipu_hwmod = {
1213         .name           = "ipu",
1214         .class          = &omap44xx_ipu_hwmod_class,
1215         .clkdm_name     = "ducati_clkdm",
1216         .rst_lines      = omap44xx_ipu_resets,
1217         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1218         .main_clk       = "ducati_clk_mux_ck",
1219         .prcm = {
1220                 .omap4 = {
1221                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1222                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1223                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1224                         .modulemode   = MODULEMODE_HWCTRL,
1225                 },
1226         },
1227 };
1228
1229 /*
1230  * 'iss' class
1231  * external images sensor pixel data processor
1232  */
1233
1234 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1235         .rev_offs       = 0x0000,
1236         .sysc_offs      = 0x0010,
1237         /*
1238          * ISS needs 100 OCP clk cycles delay after a softreset before
1239          * accessing sysconfig again.
1240          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1241          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1242          *
1243          * TODO: Indicate errata when available.
1244          */
1245         .srst_udelay    = 2,
1246         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1247                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1248         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1249                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1250                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1251         .sysc_fields    = &omap_hwmod_sysc_type2,
1252 };
1253
1254 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1255         .name   = "iss",
1256         .sysc   = &omap44xx_iss_sysc,
1257 };
1258
1259 /* iss */
1260 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1261         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1262 };
1263
1264 static struct omap_hwmod omap44xx_iss_hwmod = {
1265         .name           = "iss",
1266         .class          = &omap44xx_iss_hwmod_class,
1267         .clkdm_name     = "iss_clkdm",
1268         .main_clk       = "ducati_clk_mux_ck",
1269         .prcm = {
1270                 .omap4 = {
1271                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1272                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1273                         .modulemode   = MODULEMODE_SWCTRL,
1274                 },
1275         },
1276         .opt_clks       = iss_opt_clks,
1277         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1278 };
1279
1280 /*
1281  * 'iva' class
1282  * multi-standard video encoder/decoder hardware accelerator
1283  */
1284
1285 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1286         .name   = "iva",
1287 };
1288
1289 /* iva */
1290 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1291         { .name = "seq0", .rst_shift = 0 },
1292         { .name = "seq1", .rst_shift = 1 },
1293         { .name = "logic", .rst_shift = 2 },
1294 };
1295
1296 static struct omap_hwmod omap44xx_iva_hwmod = {
1297         .name           = "iva",
1298         .class          = &omap44xx_iva_hwmod_class,
1299         .clkdm_name     = "ivahd_clkdm",
1300         .rst_lines      = omap44xx_iva_resets,
1301         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1302         .main_clk       = "dpll_iva_m5x2_ck",
1303         .prcm = {
1304                 .omap4 = {
1305                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1306                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1307                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1308                         .modulemode   = MODULEMODE_HWCTRL,
1309                 },
1310         },
1311 };
1312
1313 /*
1314  * 'kbd' class
1315  * keyboard controller
1316  */
1317
1318 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1319         .rev_offs       = 0x0000,
1320         .sysc_offs      = 0x0010,
1321         .syss_offs      = 0x0014,
1322         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1323                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1324                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1325                            SYSS_HAS_RESET_STATUS),
1326         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1327         .sysc_fields    = &omap_hwmod_sysc_type1,
1328 };
1329
1330 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1331         .name   = "kbd",
1332         .sysc   = &omap44xx_kbd_sysc,
1333 };
1334
1335 /* kbd */
1336 static struct omap_hwmod omap44xx_kbd_hwmod = {
1337         .name           = "kbd",
1338         .class          = &omap44xx_kbd_hwmod_class,
1339         .clkdm_name     = "l4_wkup_clkdm",
1340         .main_clk       = "sys_32k_ck",
1341         .prcm = {
1342                 .omap4 = {
1343                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1344                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1345                         .modulemode   = MODULEMODE_SWCTRL,
1346                 },
1347         },
1348 };
1349
1350 /*
1351  * 'mailbox' class
1352  * mailbox module allowing communication between the on-chip processors using a
1353  * queued mailbox-interrupt mechanism.
1354  */
1355
1356 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1357         .rev_offs       = 0x0000,
1358         .sysc_offs      = 0x0010,
1359         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1360                            SYSC_HAS_SOFTRESET),
1361         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1362         .sysc_fields    = &omap_hwmod_sysc_type2,
1363 };
1364
1365 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1366         .name   = "mailbox",
1367         .sysc   = &omap44xx_mailbox_sysc,
1368 };
1369
1370 /* mailbox */
1371 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1372         .name           = "mailbox",
1373         .class          = &omap44xx_mailbox_hwmod_class,
1374         .clkdm_name     = "l4_cfg_clkdm",
1375         .prcm = {
1376                 .omap4 = {
1377                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1378                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1379                 },
1380         },
1381 };
1382
1383 /*
1384  * 'mcasp' class
1385  * multi-channel audio serial port controller
1386  */
1387
1388 /* The IP is not compliant to type1 / type2 scheme */
1389 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1390         .rev_offs       = 0,
1391         .sysc_offs      = 0x0004,
1392         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1393         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1394                            SIDLE_SMART_WKUP),
1395         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1396 };
1397
1398 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1399         .name   = "mcasp",
1400         .sysc   = &omap44xx_mcasp_sysc,
1401 };
1402
1403 /* mcasp */
1404 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1405         .name           = "mcasp",
1406         .class          = &omap44xx_mcasp_hwmod_class,
1407         .clkdm_name     = "abe_clkdm",
1408         .main_clk       = "func_mcasp_abe_gfclk",
1409         .prcm = {
1410                 .omap4 = {
1411                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1412                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_SWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'mcbsp' class
1420  * multi channel buffered serial port controller
1421  */
1422
1423 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1424         .rev_offs       = -ENODEV,
1425         .sysc_offs      = 0x008c,
1426         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1427                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1428         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1429         .sysc_fields    = &omap_hwmod_sysc_type1,
1430 };
1431
1432 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1433         .name   = "mcbsp",
1434         .sysc   = &omap44xx_mcbsp_sysc,
1435 };
1436
1437 /* mcbsp1 */
1438 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1439         { .role = "pad_fck", .clk = "pad_clks_ck" },
1440         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1441 };
1442
1443 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1444         .name           = "mcbsp1",
1445         .class          = &omap44xx_mcbsp_hwmod_class,
1446         .clkdm_name     = "abe_clkdm",
1447         .main_clk       = "func_mcbsp1_gfclk",
1448         .prcm = {
1449                 .omap4 = {
1450                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1451                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1452                         .modulemode   = MODULEMODE_SWCTRL,
1453                 },
1454         },
1455         .opt_clks       = mcbsp1_opt_clks,
1456         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1457 };
1458
1459 /* mcbsp2 */
1460 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1461         { .role = "pad_fck", .clk = "pad_clks_ck" },
1462         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1463 };
1464
1465 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1466         .name           = "mcbsp2",
1467         .class          = &omap44xx_mcbsp_hwmod_class,
1468         .clkdm_name     = "abe_clkdm",
1469         .main_clk       = "func_mcbsp2_gfclk",
1470         .prcm = {
1471                 .omap4 = {
1472                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1473                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1474                         .modulemode   = MODULEMODE_SWCTRL,
1475                 },
1476         },
1477         .opt_clks       = mcbsp2_opt_clks,
1478         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1479 };
1480
1481 /* mcbsp3 */
1482 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1483         { .role = "pad_fck", .clk = "pad_clks_ck" },
1484         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1485 };
1486
1487 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1488         .name           = "mcbsp3",
1489         .class          = &omap44xx_mcbsp_hwmod_class,
1490         .clkdm_name     = "abe_clkdm",
1491         .main_clk       = "func_mcbsp3_gfclk",
1492         .prcm = {
1493                 .omap4 = {
1494                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1495                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1496                         .modulemode   = MODULEMODE_SWCTRL,
1497                 },
1498         },
1499         .opt_clks       = mcbsp3_opt_clks,
1500         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1501 };
1502
1503 /* mcbsp4 */
1504 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1505         { .role = "pad_fck", .clk = "pad_clks_ck" },
1506         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1507 };
1508
1509 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1510         .name           = "mcbsp4",
1511         .class          = &omap44xx_mcbsp_hwmod_class,
1512         .clkdm_name     = "l4_per_clkdm",
1513         .main_clk       = "per_mcbsp4_gfclk",
1514         .prcm = {
1515                 .omap4 = {
1516                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1517                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1518                         .modulemode   = MODULEMODE_SWCTRL,
1519                 },
1520         },
1521         .opt_clks       = mcbsp4_opt_clks,
1522         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
1523 };
1524
1525 /*
1526  * 'mcpdm' class
1527  * multi channel pdm controller (proprietary interface with phoenix power
1528  * ic)
1529  */
1530
1531 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1532         .rev_offs       = 0x0000,
1533         .sysc_offs      = 0x0010,
1534         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1535                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1536         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1537                            SIDLE_SMART_WKUP),
1538         .sysc_fields    = &omap_hwmod_sysc_type2,
1539 };
1540
1541 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1542         .name   = "mcpdm",
1543         .sysc   = &omap44xx_mcpdm_sysc,
1544 };
1545
1546 /* mcpdm */
1547 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1548         .name           = "mcpdm",
1549         .class          = &omap44xx_mcpdm_hwmod_class,
1550         .clkdm_name     = "abe_clkdm",
1551         /*
1552          * It's suspected that the McPDM requires an off-chip main
1553          * functional clock, controlled via I2C.  This IP block is
1554          * currently reset very early during boot, before I2C is
1555          * available, so it doesn't seem that we have any choice in
1556          * the kernel other than to avoid resetting it.
1557          *
1558          * Also, McPDM needs to be configured to NO_IDLE mode when it
1559          * is in used otherwise vital clocks will be gated which
1560          * results 'slow motion' audio playback.
1561          */
1562         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1563         .main_clk       = "pad_clks_ck",
1564         .prcm = {
1565                 .omap4 = {
1566                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1567                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1568                         .modulemode   = MODULEMODE_SWCTRL,
1569                 },
1570         },
1571 };
1572
1573 /*
1574  * 'mmu' class
1575  * The memory management unit performs virtual to physical address translation
1576  * for its requestors.
1577  */
1578
1579 static struct omap_hwmod_class_sysconfig mmu_sysc = {
1580         .rev_offs       = 0x000,
1581         .sysc_offs      = 0x010,
1582         .syss_offs      = 0x014,
1583         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1584                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1585         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1586         .sysc_fields    = &omap_hwmod_sysc_type1,
1587 };
1588
1589 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
1590         .name = "mmu",
1591         .sysc = &mmu_sysc,
1592 };
1593
1594 /* mmu ipu */
1595
1596 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
1597 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
1598         { .name = "mmu_cache", .rst_shift = 2 },
1599 };
1600
1601 /* l3_main_2 -> mmu_ipu */
1602 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
1603         .master         = &omap44xx_l3_main_2_hwmod,
1604         .slave          = &omap44xx_mmu_ipu_hwmod,
1605         .clk            = "l3_div_ck",
1606         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1607 };
1608
1609 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
1610         .name           = "mmu_ipu",
1611         .class          = &omap44xx_mmu_hwmod_class,
1612         .clkdm_name     = "ducati_clkdm",
1613         .rst_lines      = omap44xx_mmu_ipu_resets,
1614         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
1615         .main_clk       = "ducati_clk_mux_ck",
1616         .prcm = {
1617                 .omap4 = {
1618                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1619                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1620                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1621                         .modulemode   = MODULEMODE_HWCTRL,
1622                 },
1623         },
1624 };
1625
1626 /* mmu dsp */
1627
1628 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
1629 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
1630         { .name = "mmu_cache", .rst_shift = 1 },
1631 };
1632
1633 /* l4_cfg -> dsp */
1634 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
1635         .master         = &omap44xx_l4_cfg_hwmod,
1636         .slave          = &omap44xx_mmu_dsp_hwmod,
1637         .clk            = "l4_div_ck",
1638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1639 };
1640
1641 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
1642         .name           = "mmu_dsp",
1643         .class          = &omap44xx_mmu_hwmod_class,
1644         .clkdm_name     = "tesla_clkdm",
1645         .rst_lines      = omap44xx_mmu_dsp_resets,
1646         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
1647         .main_clk       = "dpll_iva_m4x2_ck",
1648         .prcm = {
1649                 .omap4 = {
1650                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1651                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1652                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1653                         .modulemode   = MODULEMODE_HWCTRL,
1654                 },
1655         },
1656 };
1657
1658 /*
1659  * 'mpu' class
1660  * mpu sub-system
1661  */
1662
1663 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1664         .name   = "mpu",
1665 };
1666
1667 /* mpu */
1668 static struct omap_hwmod omap44xx_mpu_hwmod = {
1669         .name           = "mpu",
1670         .class          = &omap44xx_mpu_hwmod_class,
1671         .clkdm_name     = "mpuss_clkdm",
1672         .flags          = HWMOD_INIT_NO_IDLE,
1673         .main_clk       = "dpll_mpu_m2_ck",
1674         .prcm = {
1675                 .omap4 = {
1676                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
1677                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
1678                 },
1679         },
1680 };
1681
1682 /*
1683  * 'ocmc_ram' class
1684  * top-level core on-chip ram
1685  */
1686
1687 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
1688         .name   = "ocmc_ram",
1689 };
1690
1691 /* ocmc_ram */
1692 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
1693         .name           = "ocmc_ram",
1694         .class          = &omap44xx_ocmc_ram_hwmod_class,
1695         .clkdm_name     = "l3_2_clkdm",
1696         .prcm = {
1697                 .omap4 = {
1698                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
1699                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
1700                 },
1701         },
1702 };
1703
1704 /*
1705  * 'ocp2scp' class
1706  * bridge to transform ocp interface protocol to scp (serial control port)
1707  * protocol
1708  */
1709
1710 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
1711         .rev_offs       = 0x0000,
1712         .sysc_offs      = 0x0010,
1713         .syss_offs      = 0x0014,
1714         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1715                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1716         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1717         .sysc_fields    = &omap_hwmod_sysc_type1,
1718 };
1719
1720 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
1721         .name   = "ocp2scp",
1722         .sysc   = &omap44xx_ocp2scp_sysc,
1723 };
1724
1725 /* ocp2scp_usb_phy */
1726 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
1727         .name           = "ocp2scp_usb_phy",
1728         .class          = &omap44xx_ocp2scp_hwmod_class,
1729         .clkdm_name     = "l3_init_clkdm",
1730         /*
1731          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
1732          * block as an "optional clock," and normally should never be
1733          * specified as the main_clk for an OMAP IP block.  However it
1734          * turns out that this clock is actually the main clock for
1735          * the ocp2scp_usb_phy IP block:
1736          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
1737          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
1738          * to be the best workaround.
1739          */
1740         .main_clk       = "ocp2scp_usb_phy_phy_48m",
1741         .prcm = {
1742                 .omap4 = {
1743                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
1744                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
1745                         .modulemode   = MODULEMODE_HWCTRL,
1746                 },
1747         },
1748 };
1749
1750 /*
1751  * 'prcm' class
1752  * power and reset manager (part of the prcm infrastructure) + clock manager 2
1753  * + clock manager 1 (in always on power domain) + local prm in mpu
1754  */
1755
1756 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
1757         .name   = "prcm",
1758 };
1759
1760 /* prcm_mpu */
1761 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
1762         .name           = "prcm_mpu",
1763         .class          = &omap44xx_prcm_hwmod_class,
1764         .clkdm_name     = "l4_wkup_clkdm",
1765         .flags          = HWMOD_NO_IDLEST,
1766         .prcm = {
1767                 .omap4 = {
1768                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1769                 },
1770         },
1771 };
1772
1773 /* cm_core_aon */
1774 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
1775         .name           = "cm_core_aon",
1776         .class          = &omap44xx_prcm_hwmod_class,
1777         .flags          = HWMOD_NO_IDLEST,
1778         .prcm = {
1779                 .omap4 = {
1780                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1781                 },
1782         },
1783 };
1784
1785 /* cm_core */
1786 static struct omap_hwmod omap44xx_cm_core_hwmod = {
1787         .name           = "cm_core",
1788         .class          = &omap44xx_prcm_hwmod_class,
1789         .flags          = HWMOD_NO_IDLEST,
1790         .prcm = {
1791                 .omap4 = {
1792                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1793                 },
1794         },
1795 };
1796
1797 /* prm */
1798 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
1799         { .name = "rst_global_warm_sw", .rst_shift = 0 },
1800         { .name = "rst_global_cold_sw", .rst_shift = 1 },
1801 };
1802
1803 static struct omap_hwmod omap44xx_prm_hwmod = {
1804         .name           = "prm",
1805         .class          = &omap44xx_prcm_hwmod_class,
1806         .rst_lines      = omap44xx_prm_resets,
1807         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
1808 };
1809
1810 /*
1811  * 'scrm' class
1812  * system clock and reset manager
1813  */
1814
1815 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
1816         .name   = "scrm",
1817 };
1818
1819 /* scrm */
1820 static struct omap_hwmod omap44xx_scrm_hwmod = {
1821         .name           = "scrm",
1822         .class          = &omap44xx_scrm_hwmod_class,
1823         .clkdm_name     = "l4_wkup_clkdm",
1824         .prcm = {
1825                 .omap4 = {
1826                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1827                 },
1828         },
1829 };
1830
1831 /*
1832  * 'sl2if' class
1833  * shared level 2 memory interface
1834  */
1835
1836 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
1837         .name   = "sl2if",
1838 };
1839
1840 /* sl2if */
1841 static struct omap_hwmod omap44xx_sl2if_hwmod = {
1842         .name           = "sl2if",
1843         .class          = &omap44xx_sl2if_hwmod_class,
1844         .clkdm_name     = "ivahd_clkdm",
1845         .prcm = {
1846                 .omap4 = {
1847                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
1848                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
1849                         .modulemode   = MODULEMODE_HWCTRL,
1850                 },
1851         },
1852 };
1853
1854 /*
1855  * 'slimbus' class
1856  * bidirectional, multi-drop, multi-channel two-line serial interface between
1857  * the device and external components
1858  */
1859
1860 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
1861         .rev_offs       = 0x0000,
1862         .sysc_offs      = 0x0010,
1863         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1864                            SYSC_HAS_SOFTRESET),
1865         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1866                            SIDLE_SMART_WKUP),
1867         .sysc_fields    = &omap_hwmod_sysc_type2,
1868 };
1869
1870 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
1871         .name   = "slimbus",
1872         .sysc   = &omap44xx_slimbus_sysc,
1873 };
1874
1875 /* slimbus1 */
1876 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
1877         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
1878         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
1879         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
1880         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
1881 };
1882
1883 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
1884         .name           = "slimbus1",
1885         .class          = &omap44xx_slimbus_hwmod_class,
1886         .clkdm_name     = "abe_clkdm",
1887         .prcm = {
1888                 .omap4 = {
1889                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
1890                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
1891                         .modulemode   = MODULEMODE_SWCTRL,
1892                 },
1893         },
1894         .opt_clks       = slimbus1_opt_clks,
1895         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
1896 };
1897
1898 /* slimbus2 */
1899 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
1900         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
1901         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
1902         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
1903 };
1904
1905 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
1906         .name           = "slimbus2",
1907         .class          = &omap44xx_slimbus_hwmod_class,
1908         .clkdm_name     = "l4_per_clkdm",
1909         .prcm = {
1910                 .omap4 = {
1911                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
1912                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
1913                         .modulemode   = MODULEMODE_SWCTRL,
1914                 },
1915         },
1916         .opt_clks       = slimbus2_opt_clks,
1917         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
1918 };
1919
1920 /*
1921  * 'smartreflex' class
1922  * smartreflex module (monitor silicon performance and outputs a measure of
1923  * performance error)
1924  */
1925
1926 /* The IP is not compliant to type1 / type2 scheme */
1927 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1928         .rev_offs       = -ENODEV,
1929         .sysc_offs      = 0x0038,
1930         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1931         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1932                            SIDLE_SMART_WKUP),
1933         .sysc_fields    = &omap36xx_sr_sysc_fields,
1934 };
1935
1936 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1937         .name   = "smartreflex",
1938         .sysc   = &omap44xx_smartreflex_sysc,
1939 };
1940
1941 /* smartreflex_core */
1942 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1943         .sensor_voltdm_name   = "core",
1944 };
1945
1946 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1947         .name           = "smartreflex_core",
1948         .class          = &omap44xx_smartreflex_hwmod_class,
1949         .clkdm_name     = "l4_ao_clkdm",
1950
1951         .main_clk       = "smartreflex_core_fck",
1952         .prcm = {
1953                 .omap4 = {
1954                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
1955                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
1956                         .modulemode   = MODULEMODE_SWCTRL,
1957                 },
1958         },
1959         .dev_attr       = &smartreflex_core_dev_attr,
1960 };
1961
1962 /* smartreflex_iva */
1963 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
1964         .sensor_voltdm_name     = "iva",
1965 };
1966
1967 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1968         .name           = "smartreflex_iva",
1969         .class          = &omap44xx_smartreflex_hwmod_class,
1970         .clkdm_name     = "l4_ao_clkdm",
1971         .main_clk       = "smartreflex_iva_fck",
1972         .prcm = {
1973                 .omap4 = {
1974                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
1975                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
1976                         .modulemode   = MODULEMODE_SWCTRL,
1977                 },
1978         },
1979         .dev_attr       = &smartreflex_iva_dev_attr,
1980 };
1981
1982 /* smartreflex_mpu */
1983 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1984         .sensor_voltdm_name     = "mpu",
1985 };
1986
1987 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1988         .name           = "smartreflex_mpu",
1989         .class          = &omap44xx_smartreflex_hwmod_class,
1990         .clkdm_name     = "l4_ao_clkdm",
1991         .main_clk       = "smartreflex_mpu_fck",
1992         .prcm = {
1993                 .omap4 = {
1994                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
1995                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
1996                         .modulemode   = MODULEMODE_SWCTRL,
1997                 },
1998         },
1999         .dev_attr       = &smartreflex_mpu_dev_attr,
2000 };
2001
2002 /*
2003  * 'spinlock' class
2004  * spinlock provides hardware assistance for synchronizing the processes
2005  * running on multiple processors
2006  */
2007
2008 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2009         .rev_offs       = 0x0000,
2010         .sysc_offs      = 0x0010,
2011         .syss_offs      = 0x0014,
2012         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2013                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2014                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2015         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2016         .sysc_fields    = &omap_hwmod_sysc_type1,
2017 };
2018
2019 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2020         .name   = "spinlock",
2021         .sysc   = &omap44xx_spinlock_sysc,
2022 };
2023
2024 /* spinlock */
2025 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2026         .name           = "spinlock",
2027         .class          = &omap44xx_spinlock_hwmod_class,
2028         .clkdm_name     = "l4_cfg_clkdm",
2029         .prcm = {
2030                 .omap4 = {
2031                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2032                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2033                 },
2034         },
2035 };
2036
2037 /*
2038  * 'timer' class
2039  * general purpose timer module with accurate 1ms tick
2040  * This class contains several variants: ['timer_1ms', 'timer']
2041  */
2042
2043 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2044         .rev_offs       = 0x0000,
2045         .sysc_offs      = 0x0010,
2046         .syss_offs      = 0x0014,
2047         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2048                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2049                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2050                            SYSS_HAS_RESET_STATUS),
2051         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2052         .sysc_fields    = &omap_hwmod_sysc_type1,
2053 };
2054
2055 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2056         .name   = "timer",
2057         .sysc   = &omap44xx_timer_1ms_sysc,
2058 };
2059
2060 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2061         .rev_offs       = 0x0000,
2062         .sysc_offs      = 0x0010,
2063         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2064                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2065         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2066                            SIDLE_SMART_WKUP),
2067         .sysc_fields    = &omap_hwmod_sysc_type2,
2068 };
2069
2070 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2071         .name   = "timer",
2072         .sysc   = &omap44xx_timer_sysc,
2073 };
2074
2075 /* timer1 */
2076 static struct omap_hwmod omap44xx_timer1_hwmod = {
2077         .name           = "timer1",
2078         .class          = &omap44xx_timer_1ms_hwmod_class,
2079         .clkdm_name     = "l4_wkup_clkdm",
2080         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2081         .main_clk       = "dmt1_clk_mux",
2082         .prcm = {
2083                 .omap4 = {
2084                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2085                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2086                         .modulemode   = MODULEMODE_SWCTRL,
2087                 },
2088         },
2089 };
2090
2091 /* timer2 */
2092 static struct omap_hwmod omap44xx_timer2_hwmod = {
2093         .name           = "timer2",
2094         .class          = &omap44xx_timer_1ms_hwmod_class,
2095         .clkdm_name     = "l4_per_clkdm",
2096         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2097         .main_clk       = "cm2_dm2_mux",
2098         .prcm = {
2099                 .omap4 = {
2100                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2101                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2102                         .modulemode   = MODULEMODE_SWCTRL,
2103                 },
2104         },
2105 };
2106
2107 /* timer3 */
2108 static struct omap_hwmod omap44xx_timer3_hwmod = {
2109         .name           = "timer3",
2110         .class          = &omap44xx_timer_hwmod_class,
2111         .clkdm_name     = "l4_per_clkdm",
2112         .main_clk       = "cm2_dm3_mux",
2113         .prcm = {
2114                 .omap4 = {
2115                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2116                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2117                         .modulemode   = MODULEMODE_SWCTRL,
2118                 },
2119         },
2120 };
2121
2122 /* timer4 */
2123 static struct omap_hwmod omap44xx_timer4_hwmod = {
2124         .name           = "timer4",
2125         .class          = &omap44xx_timer_hwmod_class,
2126         .clkdm_name     = "l4_per_clkdm",
2127         .main_clk       = "cm2_dm4_mux",
2128         .prcm = {
2129                 .omap4 = {
2130                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2131                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2132                         .modulemode   = MODULEMODE_SWCTRL,
2133                 },
2134         },
2135 };
2136
2137 /* timer5 */
2138 static struct omap_hwmod omap44xx_timer5_hwmod = {
2139         .name           = "timer5",
2140         .class          = &omap44xx_timer_hwmod_class,
2141         .clkdm_name     = "abe_clkdm",
2142         .main_clk       = "timer5_sync_mux",
2143         .prcm = {
2144                 .omap4 = {
2145                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2146                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2147                         .modulemode   = MODULEMODE_SWCTRL,
2148                 },
2149         },
2150 };
2151
2152 /* timer6 */
2153 static struct omap_hwmod omap44xx_timer6_hwmod = {
2154         .name           = "timer6",
2155         .class          = &omap44xx_timer_hwmod_class,
2156         .clkdm_name     = "abe_clkdm",
2157         .main_clk       = "timer6_sync_mux",
2158         .prcm = {
2159                 .omap4 = {
2160                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2161                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2162                         .modulemode   = MODULEMODE_SWCTRL,
2163                 },
2164         },
2165 };
2166
2167 /* timer7 */
2168 static struct omap_hwmod omap44xx_timer7_hwmod = {
2169         .name           = "timer7",
2170         .class          = &omap44xx_timer_hwmod_class,
2171         .clkdm_name     = "abe_clkdm",
2172         .main_clk       = "timer7_sync_mux",
2173         .prcm = {
2174                 .omap4 = {
2175                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2176                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2177                         .modulemode   = MODULEMODE_SWCTRL,
2178                 },
2179         },
2180 };
2181
2182 /* timer8 */
2183 static struct omap_hwmod omap44xx_timer8_hwmod = {
2184         .name           = "timer8",
2185         .class          = &omap44xx_timer_hwmod_class,
2186         .clkdm_name     = "abe_clkdm",
2187         .main_clk       = "timer8_sync_mux",
2188         .prcm = {
2189                 .omap4 = {
2190                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2191                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2192                         .modulemode   = MODULEMODE_SWCTRL,
2193                 },
2194         },
2195 };
2196
2197 /* timer9 */
2198 static struct omap_hwmod omap44xx_timer9_hwmod = {
2199         .name           = "timer9",
2200         .class          = &omap44xx_timer_hwmod_class,
2201         .clkdm_name     = "l4_per_clkdm",
2202         .main_clk       = "cm2_dm9_mux",
2203         .prcm = {
2204                 .omap4 = {
2205                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2206                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2207                         .modulemode   = MODULEMODE_SWCTRL,
2208                 },
2209         },
2210 };
2211
2212 /* timer10 */
2213 static struct omap_hwmod omap44xx_timer10_hwmod = {
2214         .name           = "timer10",
2215         .class          = &omap44xx_timer_1ms_hwmod_class,
2216         .clkdm_name     = "l4_per_clkdm",
2217         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2218         .main_clk       = "cm2_dm10_mux",
2219         .prcm = {
2220                 .omap4 = {
2221                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2222                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2223                         .modulemode   = MODULEMODE_SWCTRL,
2224                 },
2225         },
2226 };
2227
2228 /* timer11 */
2229 static struct omap_hwmod omap44xx_timer11_hwmod = {
2230         .name           = "timer11",
2231         .class          = &omap44xx_timer_hwmod_class,
2232         .clkdm_name     = "l4_per_clkdm",
2233         .main_clk       = "cm2_dm11_mux",
2234         .prcm = {
2235                 .omap4 = {
2236                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2237                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2238                         .modulemode   = MODULEMODE_SWCTRL,
2239                 },
2240         },
2241 };
2242
2243 /*
2244  * 'usb_host_fs' class
2245  * full-speed usb host controller
2246  */
2247
2248 /* The IP is not compliant to type1 / type2 scheme */
2249 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2250         .rev_offs       = 0x0000,
2251         .sysc_offs      = 0x0210,
2252         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2253                            SYSC_HAS_SOFTRESET),
2254         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2255                            SIDLE_SMART_WKUP),
2256         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
2257 };
2258
2259 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2260         .name   = "usb_host_fs",
2261         .sysc   = &omap44xx_usb_host_fs_sysc,
2262 };
2263
2264 /* usb_host_fs */
2265 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2266         .name           = "usb_host_fs",
2267         .class          = &omap44xx_usb_host_fs_hwmod_class,
2268         .clkdm_name     = "l3_init_clkdm",
2269         .main_clk       = "usb_host_fs_fck",
2270         .prcm = {
2271                 .omap4 = {
2272                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2273                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2274                         .modulemode   = MODULEMODE_SWCTRL,
2275                 },
2276         },
2277 };
2278
2279 /*
2280  * 'usb_host_hs' class
2281  * high-speed multi-port usb host controller
2282  */
2283
2284 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2285         .rev_offs       = 0x0000,
2286         .sysc_offs      = 0x0010,
2287         .syss_offs      = 0x0014,
2288         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2289                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2290         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2291                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2292                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2293         .sysc_fields    = &omap_hwmod_sysc_type2,
2294 };
2295
2296 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2297         .name   = "usb_host_hs",
2298         .sysc   = &omap44xx_usb_host_hs_sysc,
2299 };
2300
2301 /* usb_host_hs */
2302 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2303         .name           = "usb_host_hs",
2304         .class          = &omap44xx_usb_host_hs_hwmod_class,
2305         .clkdm_name     = "l3_init_clkdm",
2306         .main_clk       = "usb_host_hs_fck",
2307         .prcm = {
2308                 .omap4 = {
2309                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2310                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2311                         .modulemode   = MODULEMODE_SWCTRL,
2312                 },
2313         },
2314
2315         /*
2316          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2317          * id: i660
2318          *
2319          * Description:
2320          * In the following configuration :
2321          * - USBHOST module is set to smart-idle mode
2322          * - PRCM asserts idle_req to the USBHOST module ( This typically
2323          *   happens when the system is going to a low power mode : all ports
2324          *   have been suspended, the master part of the USBHOST module has
2325          *   entered the standby state, and SW has cut the functional clocks)
2326          * - an USBHOST interrupt occurs before the module is able to answer
2327          *   idle_ack, typically a remote wakeup IRQ.
2328          * Then the USB HOST module will enter a deadlock situation where it
2329          * is no more accessible nor functional.
2330          *
2331          * Workaround:
2332          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2333          */
2334
2335         /*
2336          * Errata: USB host EHCI may stall when entering smart-standby mode
2337          * Id: i571
2338          *
2339          * Description:
2340          * When the USBHOST module is set to smart-standby mode, and when it is
2341          * ready to enter the standby state (i.e. all ports are suspended and
2342          * all attached devices are in suspend mode), then it can wrongly assert
2343          * the Mstandby signal too early while there are still some residual OCP
2344          * transactions ongoing. If this condition occurs, the internal state
2345          * machine may go to an undefined state and the USB link may be stuck
2346          * upon the next resume.
2347          *
2348          * Workaround:
2349          * Don't use smart standby; use only force standby,
2350          * hence HWMOD_SWSUP_MSTANDBY
2351          */
2352
2353         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2354 };
2355
2356 /*
2357  * 'usb_otg_hs' class
2358  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2359  */
2360
2361 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2362         .rev_offs       = 0x0400,
2363         .sysc_offs      = 0x0404,
2364         .syss_offs      = 0x0408,
2365         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2366                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2367                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2368         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2369                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2370                            MSTANDBY_SMART),
2371         .sysc_fields    = &omap_hwmod_sysc_type1,
2372 };
2373
2374 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2375         .name   = "usb_otg_hs",
2376         .sysc   = &omap44xx_usb_otg_hs_sysc,
2377 };
2378
2379 /* usb_otg_hs */
2380 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
2381         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
2382 };
2383
2384 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
2385         .name           = "usb_otg_hs",
2386         .class          = &omap44xx_usb_otg_hs_hwmod_class,
2387         .clkdm_name     = "l3_init_clkdm",
2388         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2389         .main_clk       = "usb_otg_hs_ick",
2390         .prcm = {
2391                 .omap4 = {
2392                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
2393                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
2394                         .modulemode   = MODULEMODE_HWCTRL,
2395                 },
2396         },
2397         .opt_clks       = usb_otg_hs_opt_clks,
2398         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
2399 };
2400
2401 /*
2402  * 'usb_tll_hs' class
2403  * usb_tll_hs module is the adapter on the usb_host_hs ports
2404  */
2405
2406 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
2407         .rev_offs       = 0x0000,
2408         .sysc_offs      = 0x0010,
2409         .syss_offs      = 0x0014,
2410         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2411                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2412                            SYSC_HAS_AUTOIDLE),
2413         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2414         .sysc_fields    = &omap_hwmod_sysc_type1,
2415 };
2416
2417 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
2418         .name   = "usb_tll_hs",
2419         .sysc   = &omap44xx_usb_tll_hs_sysc,
2420 };
2421
2422 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
2423         .name           = "usb_tll_hs",
2424         .class          = &omap44xx_usb_tll_hs_hwmod_class,
2425         .clkdm_name     = "l3_init_clkdm",
2426         .main_clk       = "usb_tll_hs_ick",
2427         .prcm = {
2428                 .omap4 = {
2429                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
2430                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
2431                         .modulemode   = MODULEMODE_HWCTRL,
2432                 },
2433         },
2434 };
2435
2436 /*
2437  * 'wd_timer' class
2438  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
2439  * overflow condition
2440  */
2441
2442 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
2443         .rev_offs       = 0x0000,
2444         .sysc_offs      = 0x0010,
2445         .syss_offs      = 0x0014,
2446         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2447                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2448         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2449                            SIDLE_SMART_WKUP),
2450         .sysc_fields    = &omap_hwmod_sysc_type1,
2451 };
2452
2453 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
2454         .name           = "wd_timer",
2455         .sysc           = &omap44xx_wd_timer_sysc,
2456         .pre_shutdown   = &omap2_wd_timer_disable,
2457         .reset          = &omap2_wd_timer_reset,
2458 };
2459
2460 /* wd_timer2 */
2461 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
2462         .name           = "wd_timer2",
2463         .class          = &omap44xx_wd_timer_hwmod_class,
2464         .clkdm_name     = "l4_wkup_clkdm",
2465         .main_clk       = "sys_32k_ck",
2466         .prcm = {
2467                 .omap4 = {
2468                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
2469                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
2470                         .modulemode   = MODULEMODE_SWCTRL,
2471                 },
2472         },
2473 };
2474
2475 /* wd_timer3 */
2476 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
2477         .name           = "wd_timer3",
2478         .class          = &omap44xx_wd_timer_hwmod_class,
2479         .clkdm_name     = "abe_clkdm",
2480         .main_clk       = "sys_32k_ck",
2481         .prcm = {
2482                 .omap4 = {
2483                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
2484                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
2485                         .modulemode   = MODULEMODE_SWCTRL,
2486                 },
2487         },
2488 };
2489
2490
2491 /*
2492  * interfaces
2493  */
2494
2495 /* l3_main_1 -> dmm */
2496 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
2497         .master         = &omap44xx_l3_main_1_hwmod,
2498         .slave          = &omap44xx_dmm_hwmod,
2499         .clk            = "l3_div_ck",
2500         .user           = OCP_USER_SDMA,
2501 };
2502
2503 /* mpu -> dmm */
2504 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
2505         .master         = &omap44xx_mpu_hwmod,
2506         .slave          = &omap44xx_dmm_hwmod,
2507         .clk            = "l3_div_ck",
2508         .user           = OCP_USER_MPU,
2509 };
2510
2511 /* iva -> l3_instr */
2512 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
2513         .master         = &omap44xx_iva_hwmod,
2514         .slave          = &omap44xx_l3_instr_hwmod,
2515         .clk            = "l3_div_ck",
2516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2517 };
2518
2519 /* l3_main_3 -> l3_instr */
2520 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
2521         .master         = &omap44xx_l3_main_3_hwmod,
2522         .slave          = &omap44xx_l3_instr_hwmod,
2523         .clk            = "l3_div_ck",
2524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 /* ocp_wp_noc -> l3_instr */
2528 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
2529         .master         = &omap44xx_ocp_wp_noc_hwmod,
2530         .slave          = &omap44xx_l3_instr_hwmod,
2531         .clk            = "l3_div_ck",
2532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2533 };
2534
2535 /* dsp -> l3_main_1 */
2536 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
2537         .master         = &omap44xx_dsp_hwmod,
2538         .slave          = &omap44xx_l3_main_1_hwmod,
2539         .clk            = "l3_div_ck",
2540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2541 };
2542
2543 /* dss -> l3_main_1 */
2544 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
2545         .master         = &omap44xx_dss_hwmod,
2546         .slave          = &omap44xx_l3_main_1_hwmod,
2547         .clk            = "l3_div_ck",
2548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2549 };
2550
2551 /* l3_main_2 -> l3_main_1 */
2552 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
2553         .master         = &omap44xx_l3_main_2_hwmod,
2554         .slave          = &omap44xx_l3_main_1_hwmod,
2555         .clk            = "l3_div_ck",
2556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2557 };
2558
2559 /* l4_cfg -> l3_main_1 */
2560 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
2561         .master         = &omap44xx_l4_cfg_hwmod,
2562         .slave          = &omap44xx_l3_main_1_hwmod,
2563         .clk            = "l4_div_ck",
2564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2565 };
2566
2567 /* mpu -> l3_main_1 */
2568 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
2569         .master         = &omap44xx_mpu_hwmod,
2570         .slave          = &omap44xx_l3_main_1_hwmod,
2571         .clk            = "l3_div_ck",
2572         .user           = OCP_USER_MPU,
2573 };
2574
2575 /* debugss -> l3_main_2 */
2576 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
2577         .master         = &omap44xx_debugss_hwmod,
2578         .slave          = &omap44xx_l3_main_2_hwmod,
2579         .clk            = "dbgclk_mux_ck",
2580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2581 };
2582
2583 /* dma_system -> l3_main_2 */
2584 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
2585         .master         = &omap44xx_dma_system_hwmod,
2586         .slave          = &omap44xx_l3_main_2_hwmod,
2587         .clk            = "l3_div_ck",
2588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2589 };
2590
2591 /* fdif -> l3_main_2 */
2592 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
2593         .master         = &omap44xx_fdif_hwmod,
2594         .slave          = &omap44xx_l3_main_2_hwmod,
2595         .clk            = "l3_div_ck",
2596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 /* gpu -> l3_main_2 */
2600 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
2601         .master         = &omap44xx_gpu_hwmod,
2602         .slave          = &omap44xx_l3_main_2_hwmod,
2603         .clk            = "l3_div_ck",
2604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2605 };
2606
2607 /* hsi -> l3_main_2 */
2608 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
2609         .master         = &omap44xx_hsi_hwmod,
2610         .slave          = &omap44xx_l3_main_2_hwmod,
2611         .clk            = "l3_div_ck",
2612         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2613 };
2614
2615 /* ipu -> l3_main_2 */
2616 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
2617         .master         = &omap44xx_ipu_hwmod,
2618         .slave          = &omap44xx_l3_main_2_hwmod,
2619         .clk            = "l3_div_ck",
2620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 /* iss -> l3_main_2 */
2624 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
2625         .master         = &omap44xx_iss_hwmod,
2626         .slave          = &omap44xx_l3_main_2_hwmod,
2627         .clk            = "l3_div_ck",
2628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2629 };
2630
2631 /* iva -> l3_main_2 */
2632 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
2633         .master         = &omap44xx_iva_hwmod,
2634         .slave          = &omap44xx_l3_main_2_hwmod,
2635         .clk            = "l3_div_ck",
2636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2637 };
2638
2639 /* l3_main_1 -> l3_main_2 */
2640 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
2641         .master         = &omap44xx_l3_main_1_hwmod,
2642         .slave          = &omap44xx_l3_main_2_hwmod,
2643         .clk            = "l3_div_ck",
2644         .user           = OCP_USER_MPU,
2645 };
2646
2647 /* l4_cfg -> l3_main_2 */
2648 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
2649         .master         = &omap44xx_l4_cfg_hwmod,
2650         .slave          = &omap44xx_l3_main_2_hwmod,
2651         .clk            = "l4_div_ck",
2652         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2653 };
2654
2655 /* usb_host_fs -> l3_main_2 */
2656 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
2657         .master         = &omap44xx_usb_host_fs_hwmod,
2658         .slave          = &omap44xx_l3_main_2_hwmod,
2659         .clk            = "l3_div_ck",
2660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2661 };
2662
2663 /* usb_host_hs -> l3_main_2 */
2664 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
2665         .master         = &omap44xx_usb_host_hs_hwmod,
2666         .slave          = &omap44xx_l3_main_2_hwmod,
2667         .clk            = "l3_div_ck",
2668         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2669 };
2670
2671 /* usb_otg_hs -> l3_main_2 */
2672 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
2673         .master         = &omap44xx_usb_otg_hs_hwmod,
2674         .slave          = &omap44xx_l3_main_2_hwmod,
2675         .clk            = "l3_div_ck",
2676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2677 };
2678
2679 /* l3_main_1 -> l3_main_3 */
2680 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
2681         .master         = &omap44xx_l3_main_1_hwmod,
2682         .slave          = &omap44xx_l3_main_3_hwmod,
2683         .clk            = "l3_div_ck",
2684         .user           = OCP_USER_MPU,
2685 };
2686
2687 /* l3_main_2 -> l3_main_3 */
2688 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
2689         .master         = &omap44xx_l3_main_2_hwmod,
2690         .slave          = &omap44xx_l3_main_3_hwmod,
2691         .clk            = "l3_div_ck",
2692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2693 };
2694
2695 /* l4_cfg -> l3_main_3 */
2696 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
2697         .master         = &omap44xx_l4_cfg_hwmod,
2698         .slave          = &omap44xx_l3_main_3_hwmod,
2699         .clk            = "l4_div_ck",
2700         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2701 };
2702
2703 /* aess -> l4_abe */
2704 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
2705         .master         = &omap44xx_aess_hwmod,
2706         .slave          = &omap44xx_l4_abe_hwmod,
2707         .clk            = "ocp_abe_iclk",
2708         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2709 };
2710
2711 /* dsp -> l4_abe */
2712 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
2713         .master         = &omap44xx_dsp_hwmod,
2714         .slave          = &omap44xx_l4_abe_hwmod,
2715         .clk            = "ocp_abe_iclk",
2716         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2717 };
2718
2719 /* l3_main_1 -> l4_abe */
2720 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
2721         .master         = &omap44xx_l3_main_1_hwmod,
2722         .slave          = &omap44xx_l4_abe_hwmod,
2723         .clk            = "l3_div_ck",
2724         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2725 };
2726
2727 /* mpu -> l4_abe */
2728 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
2729         .master         = &omap44xx_mpu_hwmod,
2730         .slave          = &omap44xx_l4_abe_hwmod,
2731         .clk            = "ocp_abe_iclk",
2732         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2733 };
2734
2735 /* l3_main_1 -> l4_cfg */
2736 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
2737         .master         = &omap44xx_l3_main_1_hwmod,
2738         .slave          = &omap44xx_l4_cfg_hwmod,
2739         .clk            = "l3_div_ck",
2740         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2741 };
2742
2743 /* l3_main_2 -> l4_per */
2744 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
2745         .master         = &omap44xx_l3_main_2_hwmod,
2746         .slave          = &omap44xx_l4_per_hwmod,
2747         .clk            = "l3_div_ck",
2748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2749 };
2750
2751 /* l4_cfg -> l4_wkup */
2752 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
2753         .master         = &omap44xx_l4_cfg_hwmod,
2754         .slave          = &omap44xx_l4_wkup_hwmod,
2755         .clk            = "l4_div_ck",
2756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2757 };
2758
2759 /* mpu -> mpu_private */
2760 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
2761         .master         = &omap44xx_mpu_hwmod,
2762         .slave          = &omap44xx_mpu_private_hwmod,
2763         .clk            = "l3_div_ck",
2764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2765 };
2766
2767 /* l4_cfg -> ocp_wp_noc */
2768 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
2769         .master         = &omap44xx_l4_cfg_hwmod,
2770         .slave          = &omap44xx_ocp_wp_noc_hwmod,
2771         .clk            = "l4_div_ck",
2772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2773 };
2774
2775 /* l4_abe -> aess */
2776 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
2777         .master         = &omap44xx_l4_abe_hwmod,
2778         .slave          = &omap44xx_aess_hwmod,
2779         .clk            = "ocp_abe_iclk",
2780         .user           = OCP_USER_MPU,
2781 };
2782
2783 /* l4_abe -> aess (dma) */
2784 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
2785         .master         = &omap44xx_l4_abe_hwmod,
2786         .slave          = &omap44xx_aess_hwmod,
2787         .clk            = "ocp_abe_iclk",
2788         .user           = OCP_USER_SDMA,
2789 };
2790
2791 /* l3_main_2 -> c2c */
2792 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
2793         .master         = &omap44xx_l3_main_2_hwmod,
2794         .slave          = &omap44xx_c2c_hwmod,
2795         .clk            = "l3_div_ck",
2796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2797 };
2798
2799 /* l4_wkup -> counter_32k */
2800 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
2801         .master         = &omap44xx_l4_wkup_hwmod,
2802         .slave          = &omap44xx_counter_32k_hwmod,
2803         .clk            = "l4_wkup_clk_mux_ck",
2804         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2805 };
2806
2807 /* l4_cfg -> ctrl_module_core */
2808 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
2809         .master         = &omap44xx_l4_cfg_hwmod,
2810         .slave          = &omap44xx_ctrl_module_core_hwmod,
2811         .clk            = "l4_div_ck",
2812         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2813 };
2814
2815 /* l4_cfg -> ctrl_module_pad_core */
2816 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
2817         .master         = &omap44xx_l4_cfg_hwmod,
2818         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
2819         .clk            = "l4_div_ck",
2820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2821 };
2822
2823 /* l4_wkup -> ctrl_module_wkup */
2824 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
2825         .master         = &omap44xx_l4_wkup_hwmod,
2826         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
2827         .clk            = "l4_wkup_clk_mux_ck",
2828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 /* l4_wkup -> ctrl_module_pad_wkup */
2832 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
2833         .master         = &omap44xx_l4_wkup_hwmod,
2834         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
2835         .clk            = "l4_wkup_clk_mux_ck",
2836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2837 };
2838
2839 /* l3_instr -> debugss */
2840 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
2841         .master         = &omap44xx_l3_instr_hwmod,
2842         .slave          = &omap44xx_debugss_hwmod,
2843         .clk            = "l3_div_ck",
2844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2845 };
2846
2847 /* l4_cfg -> dma_system */
2848 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
2849         .master         = &omap44xx_l4_cfg_hwmod,
2850         .slave          = &omap44xx_dma_system_hwmod,
2851         .clk            = "l4_div_ck",
2852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2853 };
2854
2855 /* l4_abe -> dmic */
2856 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
2857         .master         = &omap44xx_l4_abe_hwmod,
2858         .slave          = &omap44xx_dmic_hwmod,
2859         .clk            = "ocp_abe_iclk",
2860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2861 };
2862
2863 /* dsp -> iva */
2864 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
2865         .master         = &omap44xx_dsp_hwmod,
2866         .slave          = &omap44xx_iva_hwmod,
2867         .clk            = "dpll_iva_m5x2_ck",
2868         .user           = OCP_USER_DSP,
2869 };
2870
2871 /* dsp -> sl2if */
2872 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
2873         .master         = &omap44xx_dsp_hwmod,
2874         .slave          = &omap44xx_sl2if_hwmod,
2875         .clk            = "dpll_iva_m5x2_ck",
2876         .user           = OCP_USER_DSP,
2877 };
2878
2879 /* l4_cfg -> dsp */
2880 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
2881         .master         = &omap44xx_l4_cfg_hwmod,
2882         .slave          = &omap44xx_dsp_hwmod,
2883         .clk            = "l4_div_ck",
2884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2885 };
2886
2887 /* l3_main_2 -> dss */
2888 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
2889         .master         = &omap44xx_l3_main_2_hwmod,
2890         .slave          = &omap44xx_dss_hwmod,
2891         .clk            = "l3_div_ck",
2892         .user           = OCP_USER_SDMA,
2893 };
2894
2895 /* l4_per -> dss */
2896 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
2897         .master         = &omap44xx_l4_per_hwmod,
2898         .slave          = &omap44xx_dss_hwmod,
2899         .clk            = "l4_div_ck",
2900         .user           = OCP_USER_MPU,
2901 };
2902
2903 /* l3_main_2 -> dss_dispc */
2904 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
2905         .master         = &omap44xx_l3_main_2_hwmod,
2906         .slave          = &omap44xx_dss_dispc_hwmod,
2907         .clk            = "l3_div_ck",
2908         .user           = OCP_USER_SDMA,
2909 };
2910
2911 /* l4_per -> dss_dispc */
2912 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
2913         .master         = &omap44xx_l4_per_hwmod,
2914         .slave          = &omap44xx_dss_dispc_hwmod,
2915         .clk            = "l4_div_ck",
2916         .user           = OCP_USER_MPU,
2917 };
2918
2919 /* l3_main_2 -> dss_dsi1 */
2920 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
2921         .master         = &omap44xx_l3_main_2_hwmod,
2922         .slave          = &omap44xx_dss_dsi1_hwmod,
2923         .clk            = "l3_div_ck",
2924         .user           = OCP_USER_SDMA,
2925 };
2926
2927 /* l4_per -> dss_dsi1 */
2928 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
2929         .master         = &omap44xx_l4_per_hwmod,
2930         .slave          = &omap44xx_dss_dsi1_hwmod,
2931         .clk            = "l4_div_ck",
2932         .user           = OCP_USER_MPU,
2933 };
2934
2935 /* l3_main_2 -> dss_dsi2 */
2936 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
2937         .master         = &omap44xx_l3_main_2_hwmod,
2938         .slave          = &omap44xx_dss_dsi2_hwmod,
2939         .clk            = "l3_div_ck",
2940         .user           = OCP_USER_SDMA,
2941 };
2942
2943 /* l4_per -> dss_dsi2 */
2944 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
2945         .master         = &omap44xx_l4_per_hwmod,
2946         .slave          = &omap44xx_dss_dsi2_hwmod,
2947         .clk            = "l4_div_ck",
2948         .user           = OCP_USER_MPU,
2949 };
2950
2951 /* l3_main_2 -> dss_hdmi */
2952 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
2953         .master         = &omap44xx_l3_main_2_hwmod,
2954         .slave          = &omap44xx_dss_hdmi_hwmod,
2955         .clk            = "l3_div_ck",
2956         .user           = OCP_USER_SDMA,
2957 };
2958
2959 /* l4_per -> dss_hdmi */
2960 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
2961         .master         = &omap44xx_l4_per_hwmod,
2962         .slave          = &omap44xx_dss_hdmi_hwmod,
2963         .clk            = "l4_div_ck",
2964         .user           = OCP_USER_MPU,
2965 };
2966
2967 /* l3_main_2 -> dss_rfbi */
2968 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
2969         .master         = &omap44xx_l3_main_2_hwmod,
2970         .slave          = &omap44xx_dss_rfbi_hwmod,
2971         .clk            = "l3_div_ck",
2972         .user           = OCP_USER_SDMA,
2973 };
2974
2975 /* l4_per -> dss_rfbi */
2976 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
2977         .master         = &omap44xx_l4_per_hwmod,
2978         .slave          = &omap44xx_dss_rfbi_hwmod,
2979         .clk            = "l4_div_ck",
2980         .user           = OCP_USER_MPU,
2981 };
2982
2983 /* l3_main_2 -> dss_venc */
2984 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
2985         .master         = &omap44xx_l3_main_2_hwmod,
2986         .slave          = &omap44xx_dss_venc_hwmod,
2987         .clk            = "l3_div_ck",
2988         .user           = OCP_USER_SDMA,
2989 };
2990
2991 /* l4_per -> dss_venc */
2992 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
2993         .master         = &omap44xx_l4_per_hwmod,
2994         .slave          = &omap44xx_dss_venc_hwmod,
2995         .clk            = "l4_div_ck",
2996         .user           = OCP_USER_MPU,
2997 };
2998
2999 /* l3_main_2 -> sham */
3000 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
3001         .master         = &omap44xx_l3_main_2_hwmod,
3002         .slave          = &omap44xx_sha0_hwmod,
3003         .clk            = "l3_div_ck",
3004         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3005 };
3006
3007 /* l4_per -> elm */
3008 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3009         .master         = &omap44xx_l4_per_hwmod,
3010         .slave          = &omap44xx_elm_hwmod,
3011         .clk            = "l4_div_ck",
3012         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3013 };
3014
3015 /* l4_cfg -> fdif */
3016 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3017         .master         = &omap44xx_l4_cfg_hwmod,
3018         .slave          = &omap44xx_fdif_hwmod,
3019         .clk            = "l4_div_ck",
3020         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3021 };
3022
3023 /* l3_main_2 -> gpmc */
3024 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
3025         .master         = &omap44xx_l3_main_2_hwmod,
3026         .slave          = &omap44xx_gpmc_hwmod,
3027         .clk            = "l3_div_ck",
3028         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3029 };
3030
3031 /* l3_main_2 -> gpu */
3032 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
3033         .master         = &omap44xx_l3_main_2_hwmod,
3034         .slave          = &omap44xx_gpu_hwmod,
3035         .clk            = "l3_div_ck",
3036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3037 };
3038
3039 /* l4_per -> hdq1w */
3040 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
3041         .master         = &omap44xx_l4_per_hwmod,
3042         .slave          = &omap44xx_hdq1w_hwmod,
3043         .clk            = "l4_div_ck",
3044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3045 };
3046
3047 /* l4_cfg -> hsi */
3048 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
3049         .master         = &omap44xx_l4_cfg_hwmod,
3050         .slave          = &omap44xx_hsi_hwmod,
3051         .clk            = "l4_div_ck",
3052         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3053 };
3054
3055 /* l3_main_2 -> ipu */
3056 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
3057         .master         = &omap44xx_l3_main_2_hwmod,
3058         .slave          = &omap44xx_ipu_hwmod,
3059         .clk            = "l3_div_ck",
3060         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3061 };
3062
3063 /* l3_main_2 -> iss */
3064 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
3065         .master         = &omap44xx_l3_main_2_hwmod,
3066         .slave          = &omap44xx_iss_hwmod,
3067         .clk            = "l3_div_ck",
3068         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3069 };
3070
3071 /* iva -> sl2if */
3072 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
3073         .master         = &omap44xx_iva_hwmod,
3074         .slave          = &omap44xx_sl2if_hwmod,
3075         .clk            = "dpll_iva_m5x2_ck",
3076         .user           = OCP_USER_IVA,
3077 };
3078
3079 /* l3_main_2 -> iva */
3080 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
3081         .master         = &omap44xx_l3_main_2_hwmod,
3082         .slave          = &omap44xx_iva_hwmod,
3083         .clk            = "l3_div_ck",
3084         .user           = OCP_USER_MPU,
3085 };
3086
3087 /* l4_wkup -> kbd */
3088 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
3089         .master         = &omap44xx_l4_wkup_hwmod,
3090         .slave          = &omap44xx_kbd_hwmod,
3091         .clk            = "l4_wkup_clk_mux_ck",
3092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3093 };
3094
3095 /* l4_cfg -> mailbox */
3096 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
3097         .master         = &omap44xx_l4_cfg_hwmod,
3098         .slave          = &omap44xx_mailbox_hwmod,
3099         .clk            = "l4_div_ck",
3100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3101 };
3102
3103 /* l4_abe -> mcasp */
3104 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
3105         .master         = &omap44xx_l4_abe_hwmod,
3106         .slave          = &omap44xx_mcasp_hwmod,
3107         .clk            = "ocp_abe_iclk",
3108         .user           = OCP_USER_MPU,
3109 };
3110
3111 /* l4_abe -> mcasp (dma) */
3112 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
3113         .master         = &omap44xx_l4_abe_hwmod,
3114         .slave          = &omap44xx_mcasp_hwmod,
3115         .clk            = "ocp_abe_iclk",
3116         .user           = OCP_USER_SDMA,
3117 };
3118
3119 /* l4_abe -> mcbsp1 */
3120 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
3121         .master         = &omap44xx_l4_abe_hwmod,
3122         .slave          = &omap44xx_mcbsp1_hwmod,
3123         .clk            = "ocp_abe_iclk",
3124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3125 };
3126
3127 /* l4_abe -> mcbsp2 */
3128 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3129         .master         = &omap44xx_l4_abe_hwmod,
3130         .slave          = &omap44xx_mcbsp2_hwmod,
3131         .clk            = "ocp_abe_iclk",
3132         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3133 };
3134
3135 /* l4_abe -> mcbsp3 */
3136 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3137         .master         = &omap44xx_l4_abe_hwmod,
3138         .slave          = &omap44xx_mcbsp3_hwmod,
3139         .clk            = "ocp_abe_iclk",
3140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3141 };
3142
3143 /* l4_per -> mcbsp4 */
3144 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3145         .master         = &omap44xx_l4_per_hwmod,
3146         .slave          = &omap44xx_mcbsp4_hwmod,
3147         .clk            = "l4_div_ck",
3148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3149 };
3150
3151 /* l4_abe -> mcpdm */
3152 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3153         .master         = &omap44xx_l4_abe_hwmod,
3154         .slave          = &omap44xx_mcpdm_hwmod,
3155         .clk            = "ocp_abe_iclk",
3156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3157 };
3158
3159 /* l3_main_2 -> ocmc_ram */
3160 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
3161         .master         = &omap44xx_l3_main_2_hwmod,
3162         .slave          = &omap44xx_ocmc_ram_hwmod,
3163         .clk            = "l3_div_ck",
3164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3165 };
3166
3167 /* l4_cfg -> ocp2scp_usb_phy */
3168 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
3169         .master         = &omap44xx_l4_cfg_hwmod,
3170         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
3171         .clk            = "l4_div_ck",
3172         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3173 };
3174
3175 /* mpu_private -> prcm_mpu */
3176 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
3177         .master         = &omap44xx_mpu_private_hwmod,
3178         .slave          = &omap44xx_prcm_mpu_hwmod,
3179         .clk            = "l3_div_ck",
3180         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3181 };
3182
3183 /* l4_wkup -> cm_core_aon */
3184 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
3185         .master         = &omap44xx_l4_wkup_hwmod,
3186         .slave          = &omap44xx_cm_core_aon_hwmod,
3187         .clk            = "l4_wkup_clk_mux_ck",
3188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3189 };
3190
3191 /* l4_cfg -> cm_core */
3192 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
3193         .master         = &omap44xx_l4_cfg_hwmod,
3194         .slave          = &omap44xx_cm_core_hwmod,
3195         .clk            = "l4_div_ck",
3196         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3197 };
3198
3199 /* l4_wkup -> prm */
3200 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
3201         .master         = &omap44xx_l4_wkup_hwmod,
3202         .slave          = &omap44xx_prm_hwmod,
3203         .clk            = "l4_wkup_clk_mux_ck",
3204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3205 };
3206
3207 /* l4_wkup -> scrm */
3208 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
3209         .master         = &omap44xx_l4_wkup_hwmod,
3210         .slave          = &omap44xx_scrm_hwmod,
3211         .clk            = "l4_wkup_clk_mux_ck",
3212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3213 };
3214
3215 /* l3_main_2 -> sl2if */
3216 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
3217         .master         = &omap44xx_l3_main_2_hwmod,
3218         .slave          = &omap44xx_sl2if_hwmod,
3219         .clk            = "l3_div_ck",
3220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3221 };
3222
3223 /* l4_abe -> slimbus1 */
3224 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
3225         .master         = &omap44xx_l4_abe_hwmod,
3226         .slave          = &omap44xx_slimbus1_hwmod,
3227         .clk            = "ocp_abe_iclk",
3228         .user           = OCP_USER_MPU,
3229 };
3230
3231 /* l4_abe -> slimbus1 (dma) */
3232 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
3233         .master         = &omap44xx_l4_abe_hwmod,
3234         .slave          = &omap44xx_slimbus1_hwmod,
3235         .clk            = "ocp_abe_iclk",
3236         .user           = OCP_USER_SDMA,
3237 };
3238
3239 /* l4_per -> slimbus2 */
3240 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
3241         .master         = &omap44xx_l4_per_hwmod,
3242         .slave          = &omap44xx_slimbus2_hwmod,
3243         .clk            = "l4_div_ck",
3244         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3245 };
3246
3247 /* l4_cfg -> smartreflex_core */
3248 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3249         .master         = &omap44xx_l4_cfg_hwmod,
3250         .slave          = &omap44xx_smartreflex_core_hwmod,
3251         .clk            = "l4_div_ck",
3252         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3253 };
3254
3255 /* l4_cfg -> smartreflex_iva */
3256 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3257         .master         = &omap44xx_l4_cfg_hwmod,
3258         .slave          = &omap44xx_smartreflex_iva_hwmod,
3259         .clk            = "l4_div_ck",
3260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3261 };
3262
3263 /* l4_cfg -> smartreflex_mpu */
3264 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3265         .master         = &omap44xx_l4_cfg_hwmod,
3266         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3267         .clk            = "l4_div_ck",
3268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3269 };
3270
3271 /* l4_cfg -> spinlock */
3272 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3273         .master         = &omap44xx_l4_cfg_hwmod,
3274         .slave          = &omap44xx_spinlock_hwmod,
3275         .clk            = "l4_div_ck",
3276         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3277 };
3278
3279 /* l4_wkup -> timer1 */
3280 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3281         .master         = &omap44xx_l4_wkup_hwmod,
3282         .slave          = &omap44xx_timer1_hwmod,
3283         .clk            = "l4_wkup_clk_mux_ck",
3284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3285 };
3286
3287 /* l4_per -> timer2 */
3288 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
3289         .master         = &omap44xx_l4_per_hwmod,
3290         .slave          = &omap44xx_timer2_hwmod,
3291         .clk            = "l4_div_ck",
3292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3293 };
3294
3295 /* l4_per -> timer3 */
3296 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
3297         .master         = &omap44xx_l4_per_hwmod,
3298         .slave          = &omap44xx_timer3_hwmod,
3299         .clk            = "l4_div_ck",
3300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3301 };
3302
3303 /* l4_per -> timer4 */
3304 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
3305         .master         = &omap44xx_l4_per_hwmod,
3306         .slave          = &omap44xx_timer4_hwmod,
3307         .clk            = "l4_div_ck",
3308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3309 };
3310
3311 /* l4_abe -> timer5 */
3312 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
3313         .master         = &omap44xx_l4_abe_hwmod,
3314         .slave          = &omap44xx_timer5_hwmod,
3315         .clk            = "ocp_abe_iclk",
3316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3317 };
3318
3319 /* l4_abe -> timer6 */
3320 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
3321         .master         = &omap44xx_l4_abe_hwmod,
3322         .slave          = &omap44xx_timer6_hwmod,
3323         .clk            = "ocp_abe_iclk",
3324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3325 };
3326
3327 /* l4_abe -> timer7 */
3328 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
3329         .master         = &omap44xx_l4_abe_hwmod,
3330         .slave          = &omap44xx_timer7_hwmod,
3331         .clk            = "ocp_abe_iclk",
3332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3333 };
3334
3335 /* l4_abe -> timer8 */
3336 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
3337         .master         = &omap44xx_l4_abe_hwmod,
3338         .slave          = &omap44xx_timer8_hwmod,
3339         .clk            = "ocp_abe_iclk",
3340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3341 };
3342
3343 /* l4_per -> timer9 */
3344 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
3345         .master         = &omap44xx_l4_per_hwmod,
3346         .slave          = &omap44xx_timer9_hwmod,
3347         .clk            = "l4_div_ck",
3348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3349 };
3350
3351 /* l4_per -> timer10 */
3352 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
3353         .master         = &omap44xx_l4_per_hwmod,
3354         .slave          = &omap44xx_timer10_hwmod,
3355         .clk            = "l4_div_ck",
3356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3357 };
3358
3359 /* l4_per -> timer11 */
3360 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
3361         .master         = &omap44xx_l4_per_hwmod,
3362         .slave          = &omap44xx_timer11_hwmod,
3363         .clk            = "l4_div_ck",
3364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3365 };
3366
3367 /* l4_cfg -> usb_host_fs */
3368 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
3369         .master         = &omap44xx_l4_cfg_hwmod,
3370         .slave          = &omap44xx_usb_host_fs_hwmod,
3371         .clk            = "l4_div_ck",
3372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3373 };
3374
3375 /* l4_cfg -> usb_host_hs */
3376 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
3377         .master         = &omap44xx_l4_cfg_hwmod,
3378         .slave          = &omap44xx_usb_host_hs_hwmod,
3379         .clk            = "l4_div_ck",
3380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3381 };
3382
3383 /* l4_cfg -> usb_otg_hs */
3384 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
3385         .master         = &omap44xx_l4_cfg_hwmod,
3386         .slave          = &omap44xx_usb_otg_hs_hwmod,
3387         .clk            = "l4_div_ck",
3388         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3389 };
3390
3391 /* l4_cfg -> usb_tll_hs */
3392 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
3393         .master         = &omap44xx_l4_cfg_hwmod,
3394         .slave          = &omap44xx_usb_tll_hs_hwmod,
3395         .clk            = "l4_div_ck",
3396         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3397 };
3398
3399 /* l4_wkup -> wd_timer2 */
3400 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
3401         .master         = &omap44xx_l4_wkup_hwmod,
3402         .slave          = &omap44xx_wd_timer2_hwmod,
3403         .clk            = "l4_wkup_clk_mux_ck",
3404         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3405 };
3406
3407 /* l4_abe -> wd_timer3 */
3408 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
3409         .master         = &omap44xx_l4_abe_hwmod,
3410         .slave          = &omap44xx_wd_timer3_hwmod,
3411         .clk            = "ocp_abe_iclk",
3412         .user           = OCP_USER_MPU,
3413 };
3414
3415 /* l4_abe -> wd_timer3 (dma) */
3416 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
3417         .master         = &omap44xx_l4_abe_hwmod,
3418         .slave          = &omap44xx_wd_timer3_hwmod,
3419         .clk            = "ocp_abe_iclk",
3420         .user           = OCP_USER_SDMA,
3421 };
3422
3423 /* mpu -> emif1 */
3424 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
3425         .master         = &omap44xx_mpu_hwmod,
3426         .slave          = &omap44xx_emif1_hwmod,
3427         .clk            = "l3_div_ck",
3428         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3429 };
3430
3431 /* mpu -> emif2 */
3432 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
3433         .master         = &omap44xx_mpu_hwmod,
3434         .slave          = &omap44xx_emif2_hwmod,
3435         .clk            = "l3_div_ck",
3436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3437 };
3438
3439 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
3440         &omap44xx_l3_main_1__dmm,
3441         &omap44xx_mpu__dmm,
3442         &omap44xx_iva__l3_instr,
3443         &omap44xx_l3_main_3__l3_instr,
3444         &omap44xx_ocp_wp_noc__l3_instr,
3445         &omap44xx_dsp__l3_main_1,
3446         &omap44xx_dss__l3_main_1,
3447         &omap44xx_l3_main_2__l3_main_1,
3448         &omap44xx_l4_cfg__l3_main_1,
3449         &omap44xx_mpu__l3_main_1,
3450         &omap44xx_debugss__l3_main_2,
3451         &omap44xx_dma_system__l3_main_2,
3452         &omap44xx_fdif__l3_main_2,
3453         &omap44xx_gpu__l3_main_2,
3454         &omap44xx_hsi__l3_main_2,
3455         &omap44xx_ipu__l3_main_2,
3456         &omap44xx_iss__l3_main_2,
3457         &omap44xx_iva__l3_main_2,
3458         &omap44xx_l3_main_1__l3_main_2,
3459         &omap44xx_l4_cfg__l3_main_2,
3460         /* &omap44xx_usb_host_fs__l3_main_2, */
3461         &omap44xx_usb_host_hs__l3_main_2,
3462         &omap44xx_usb_otg_hs__l3_main_2,
3463         &omap44xx_l3_main_1__l3_main_3,
3464         &omap44xx_l3_main_2__l3_main_3,
3465         &omap44xx_l4_cfg__l3_main_3,
3466         &omap44xx_aess__l4_abe,
3467         &omap44xx_dsp__l4_abe,
3468         &omap44xx_l3_main_1__l4_abe,
3469         &omap44xx_mpu__l4_abe,
3470         &omap44xx_l3_main_1__l4_cfg,
3471         &omap44xx_l3_main_2__l4_per,
3472         &omap44xx_l4_cfg__l4_wkup,
3473         &omap44xx_mpu__mpu_private,
3474         &omap44xx_l4_cfg__ocp_wp_noc,
3475         &omap44xx_l4_abe__aess,
3476         &omap44xx_l4_abe__aess_dma,
3477         &omap44xx_l3_main_2__c2c,
3478         &omap44xx_l4_wkup__counter_32k,
3479         &omap44xx_l4_cfg__ctrl_module_core,
3480         &omap44xx_l4_cfg__ctrl_module_pad_core,
3481         &omap44xx_l4_wkup__ctrl_module_wkup,
3482         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
3483         &omap44xx_l3_instr__debugss,
3484         &omap44xx_l4_cfg__dma_system,
3485         &omap44xx_l4_abe__dmic,
3486         &omap44xx_dsp__iva,
3487         /* &omap44xx_dsp__sl2if, */
3488         &omap44xx_l4_cfg__dsp,
3489         &omap44xx_l3_main_2__dss,
3490         &omap44xx_l4_per__dss,
3491         &omap44xx_l3_main_2__dss_dispc,
3492         &omap44xx_l4_per__dss_dispc,
3493         &omap44xx_l3_main_2__dss_dsi1,
3494         &omap44xx_l4_per__dss_dsi1,
3495         &omap44xx_l3_main_2__dss_dsi2,
3496         &omap44xx_l4_per__dss_dsi2,
3497         &omap44xx_l3_main_2__dss_hdmi,
3498         &omap44xx_l4_per__dss_hdmi,
3499         &omap44xx_l3_main_2__dss_rfbi,
3500         &omap44xx_l4_per__dss_rfbi,
3501         &omap44xx_l3_main_2__dss_venc,
3502         &omap44xx_l4_per__dss_venc,
3503         &omap44xx_l4_per__elm,
3504         &omap44xx_l4_cfg__fdif,
3505         &omap44xx_l3_main_2__gpmc,
3506         &omap44xx_l3_main_2__gpu,
3507         &omap44xx_l4_per__hdq1w,
3508         &omap44xx_l4_cfg__hsi,
3509         &omap44xx_l3_main_2__ipu,
3510         &omap44xx_l3_main_2__iss,
3511         /* &omap44xx_iva__sl2if, */
3512         &omap44xx_l3_main_2__iva,
3513         &omap44xx_l4_wkup__kbd,
3514         &omap44xx_l4_cfg__mailbox,
3515         &omap44xx_l4_abe__mcasp,
3516         &omap44xx_l4_abe__mcasp_dma,
3517         &omap44xx_l4_abe__mcbsp1,
3518         &omap44xx_l4_abe__mcbsp2,
3519         &omap44xx_l4_abe__mcbsp3,
3520         &omap44xx_l4_per__mcbsp4,
3521         &omap44xx_l4_abe__mcpdm,
3522         &omap44xx_l3_main_2__mmu_ipu,
3523         &omap44xx_l4_cfg__mmu_dsp,
3524         &omap44xx_l3_main_2__ocmc_ram,
3525         &omap44xx_l4_cfg__ocp2scp_usb_phy,
3526         &omap44xx_mpu_private__prcm_mpu,
3527         &omap44xx_l4_wkup__cm_core_aon,
3528         &omap44xx_l4_cfg__cm_core,
3529         &omap44xx_l4_wkup__prm,
3530         &omap44xx_l4_wkup__scrm,
3531         /* &omap44xx_l3_main_2__sl2if, */
3532         &omap44xx_l4_abe__slimbus1,
3533         &omap44xx_l4_abe__slimbus1_dma,
3534         &omap44xx_l4_per__slimbus2,
3535         &omap44xx_l4_cfg__smartreflex_core,
3536         &omap44xx_l4_cfg__smartreflex_iva,
3537         &omap44xx_l4_cfg__smartreflex_mpu,
3538         &omap44xx_l4_cfg__spinlock,
3539         &omap44xx_l4_wkup__timer1,
3540         &omap44xx_l4_per__timer2,
3541         &omap44xx_l4_per__timer3,
3542         &omap44xx_l4_per__timer4,
3543         &omap44xx_l4_abe__timer5,
3544         &omap44xx_l4_abe__timer6,
3545         &omap44xx_l4_abe__timer7,
3546         &omap44xx_l4_abe__timer8,
3547         &omap44xx_l4_per__timer9,
3548         &omap44xx_l4_per__timer10,
3549         &omap44xx_l4_per__timer11,
3550         /* &omap44xx_l4_cfg__usb_host_fs, */
3551         &omap44xx_l4_cfg__usb_host_hs,
3552         &omap44xx_l4_cfg__usb_otg_hs,
3553         &omap44xx_l4_cfg__usb_tll_hs,
3554         &omap44xx_l4_wkup__wd_timer2,
3555         &omap44xx_l4_abe__wd_timer3,
3556         &omap44xx_l4_abe__wd_timer3_dma,
3557         &omap44xx_mpu__emif1,
3558         &omap44xx_mpu__emif2,
3559         &omap44xx_l3_main_2__aes1,
3560         &omap44xx_l3_main_2__aes2,
3561         &omap44xx_l3_main_2__des,
3562         &omap44xx_l3_main_2__sha0,
3563         NULL,
3564 };
3565
3566 int __init omap44xx_hwmod_init(void)
3567 {
3568         omap_hwmod_init();
3569         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
3570 }
3571