1 // SPDX-License-Identifier: GPL-2.0+
3 * Timing and Organization details of the Elpida parts used in OMAP4
7 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
13 #include <asm/arch/sys_proto.h>
16 * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
17 * SDP and Panda. Since the parts used and geometry are identical for
18 * SDP and Panda for a given OMAP4 revision, this information is kept
19 * here instead of being in board directory. However the key functions
20 * exported are weakly linked so that they can be over-ridden in the board
21 * directory if there is a OMAP4 board in the future that uses a different
22 * memory device or geometry.
24 * For any new board with different memory devices over-ride one or more
25 * of the following functions as per the CONFIG flags you intend to enable:
26 * - emif_get_reg_dump()
27 * - emif_get_dmm_regs()
28 * - emif_get_device_details()
29 * - emif_get_device_timings()
32 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
34 const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
35 .sdram_config_init = 0x80000eb9,
36 .sdram_config = 0x80001ab9,
37 .ref_ctrl = 0x0000030c,
38 .sdram_tim1 = 0x08648311,
39 .sdram_tim2 = 0x101b06ca,
40 .sdram_tim3 = 0x0048a19f,
41 .read_idle_ctrl = 0x000501ff,
42 .zq_config = 0x500b3214,
43 .temp_alert_config = 0xd8016893,
44 .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
45 .emif_ddr_phy_ctlr_1 = 0x049ff808
48 const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
49 .sdram_config_init = 0x80000eb1,
50 .sdram_config = 0x80001ab1,
51 .ref_ctrl = 0x000005cd,
52 .sdram_tim1 = 0x10cb0622,
53 .sdram_tim2 = 0x20350d52,
54 .sdram_tim3 = 0x00b1431f,
55 .read_idle_ctrl = 0x000501ff,
56 .zq_config = 0x500b3214,
57 .temp_alert_config = 0x58016893,
58 .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
59 .emif_ddr_phy_ctlr_1 = 0x049ff418
62 const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
63 .sdram_config_init = 0x80800eb2,
64 .sdram_config = 0x80801ab2,
65 .ref_ctrl = 0x00000618,
66 .sdram_tim1 = 0x10eb0662,
67 .sdram_tim2 = 0x20370dd2,
68 .sdram_tim3 = 0x00b1c33f,
69 .read_idle_ctrl = 0x000501ff,
70 .zq_config = 0x500b3215,
71 .temp_alert_config = 0x58016893,
72 .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
73 .emif_ddr_phy_ctlr_1 = 0x049ff418
76 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
77 .sdram_config_init = 0x80000eb9,
78 .sdram_config = 0x80001ab9,
79 .ref_ctrl = 0x00000618,
80 .sdram_tim1 = 0x10eb0662,
81 .sdram_tim2 = 0x20370dd2,
82 .sdram_tim3 = 0x00b1c33f,
83 .read_idle_ctrl = 0x000501ff,
84 .zq_config = 0xd00b3214,
85 .temp_alert_config = 0xd8016893,
86 .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
87 .emif_ddr_phy_ctlr_1 = 0x049ff418
90 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
91 .dmm_lisa_map_0 = 0xFF020100,
94 .dmm_lisa_map_3 = 0x80540300,
98 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
99 .dmm_lisa_map_0 = 0xFF020100,
102 .dmm_lisa_map_3 = 0x80640300,
106 const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
107 .dmm_lisa_map_0 = 0xFF020100,
110 .dmm_lisa_map_3 = 0x80640300,
114 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
116 u32 omap4_rev = omap_revision();
118 /* Same devices and geometry on both EMIFs */
119 if (omap4_rev == OMAP4430_ES1_0)
120 *regs = &emif_regs_elpida_380_mhz_1cs;
121 else if (omap4_rev == OMAP4430_ES2_0)
122 *regs = &emif_regs_elpida_200_mhz_2cs;
123 else if (omap4_rev < OMAP4470_ES1_0)
124 *regs = &emif_regs_elpida_400_mhz_2cs;
126 *regs = &emif_regs_elpida_400_mhz_1cs;
128 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
129 __attribute__((weak, alias("emif_get_reg_dump_sdp")));
131 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
134 u32 omap_rev = omap_revision();
136 if (omap_rev == OMAP4430_ES1_0)
137 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
138 else if (omap_rev < OMAP4460_ES1_0)
139 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
141 *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
144 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
145 __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
149 const struct lpddr2_device_details elpida_2G_S4_details = {
150 .type = LPDDR2_TYPE_S4,
151 .density = LPDDR2_DENSITY_2Gb,
152 .io_width = LPDDR2_IO_WIDTH_32,
153 .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
156 const struct lpddr2_device_details elpida_4G_S4_details = {
157 .type = LPDDR2_TYPE_S4,
158 .density = LPDDR2_DENSITY_4Gb,
159 .io_width = LPDDR2_IO_WIDTH_32,
160 .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
163 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
164 struct lpddr2_device_details *lpddr2_dev_details)
166 u32 omap_rev = omap_revision();
168 /* EMIF1 & EMIF2 have identical configuration */
169 if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
171 /* Nothing connected on CS1 for 4430/4470 ES1.0 */
173 } else if (omap_rev < OMAP4470_ES1_0) {
174 /* In all other 4430/4460 cases Elpida 2G device */
175 *lpddr2_dev_details = elpida_2G_S4_details;
177 /* 4470: 4G device */
178 *lpddr2_dev_details = elpida_4G_S4_details;
180 return lpddr2_dev_details;
183 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
184 struct lpddr2_device_details *lpddr2_dev_details)
185 __attribute__((weak, alias("emif_get_device_details_sdp")));
187 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
189 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
190 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
191 .max_freq = 400000000,
213 static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
214 .max_freq = 333000000,
236 static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
237 .max_freq = 200000000,
259 static const struct lpddr2_min_tck min_tck_elpida = {
274 static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
275 &timings_elpida_200_mhz,
276 &timings_elpida_333_mhz,
277 &timings_elpida_400_mhz
280 const struct lpddr2_device_timings elpida_2G_S4_timings = {
281 .ac_timings = elpida_ac_timings,
282 .min_tck = &min_tck_elpida,
285 void emif_get_device_timings_sdp(u32 emif_nr,
286 const struct lpddr2_device_timings **cs0_device_timings,
287 const struct lpddr2_device_timings **cs1_device_timings)
289 u32 omap_rev = omap_revision();
291 /* Identical devices on EMIF1 & EMIF2 */
292 *cs0_device_timings = &elpida_2G_S4_timings;
294 if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
295 *cs1_device_timings = NULL;
297 *cs1_device_timings = &elpida_2G_S4_timings;
300 void emif_get_device_timings(u32 emif_nr,
301 const struct lpddr2_device_timings **cs0_device_timings,
302 const struct lpddr2_device_timings **cs1_device_timings)
303 __attribute__((weak, alias("emif_get_device_timings_sdp")));
305 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
307 const struct lpddr2_mr_regs mr_regs = {
308 .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
311 .mr10 = MR10_ZQ_ZQINIT,
312 .mr16 = MR16_REF_FULL_ARRAY
315 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
320 __weak const struct read_write_regs *get_bug_regs(u32 *iterations)