arch/arm/mach-omap2/omap4/hwinit.c

   1 /*
   2  *
   3  * Common functions for OMAP4 based boards
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14 #include <common.h>
  15 #include <palmas.h>
  16 #include <asm/armv7.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <linux/sizes.h>
  20 #include <asm/emif.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/omap_common.h>
  23
  24 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  25
  26 static const struct gpio_bank gpio_bank_44xx[6] = {
  27         { (void *)OMAP44XX_GPIO1_BASE },
  28         { (void *)OMAP44XX_GPIO2_BASE },
  29         { (void *)OMAP44XX_GPIO3_BASE },
  30         { (void *)OMAP44XX_GPIO4_BASE },
  31         { (void *)OMAP44XX_GPIO5_BASE },
  32         { (void *)OMAP44XX_GPIO6_BASE },
  33 };
  34
  35 const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
  36
  37 #ifdef CONFIG_SPL_BUILD
  38 /*
  39  * Some tuning of IOs for optimal power and performance
  40  */
  41 void do_io_settings(void)
  42 {
  43         u32 lpddr2io;
  44
  45         u32 omap4_rev = omap_revision();
  46
  47         if (omap4_rev == OMAP4430_ES1_0)
  48                 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
  49         else if (omap4_rev == OMAP4430_ES2_0)
  50                 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
  51         else
  52                 lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
  53
  54         /* EMIF1 */
  55         writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
  56         writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
  57         /* No pull for GR10 as per hw team's recommendation */
  58         writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
  59                 (*ctrl)->control_lpddr2io1_2);
  60         writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
  61
  62         /* EMIF2 */
  63         writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
  64         writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
  65         /* No pull for GR10 as per hw team's recommendation */
  66         writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
  67                 (*ctrl)->control_lpddr2io2_2);
  68         writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
  69
  70         /*
  71          * Some of these settings (TRIM values) come from eFuse and are
  72          * in turn programmed in the eFuse at manufacturing time after
  73          * calibration of the device. Do the software over-ride only if
  74          * the device is not correctly trimmed
  75          */
  76         if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
  77
  78                 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
  79                         (*ctrl)->control_ldosram_iva_voltage_ctrl);
  80
  81                 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
  82                         (*ctrl)->control_ldosram_mpu_voltage_ctrl);
  83
  84                 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
  85                         (*ctrl)->control_ldosram_core_voltage_ctrl);
  86         }
  87
  88         /*
  89          * Over-ride the register
  90          *      i. unconditionally for all 4430
  91          *      ii. only if un-trimmed for 4460
  92          */
  93         if (!readl((*ctrl)->control_efuse_1))
  94                 writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
  95
  96         if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
  97                 writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
  98 }
  99 #endif /* CONFIG_SPL_BUILD */
 100
 101 /* dummy fuction for omap4 */
 102 void config_data_eye_leveling_samples(u32 emif_base)
 103 {
 104 }
 105
 106 void init_omap_revision(void)
 107 {
 108         /*
 109          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 110          * Also, ES1 and ES2 have different ARM revisions
 111          * So use ARM revision for identification
 112          */
 113         unsigned int arm_rev = cortex_rev();
 114
 115         switch (arm_rev) {
 116         case MIDR_CORTEX_A9_R0P1:
 117                 *omap_si_rev = OMAP4430_ES1_0;
 118                 break;
 119         case MIDR_CORTEX_A9_R1P2:
 120                 switch (readl(CONTROL_ID_CODE)) {
 121                 case OMAP4_CONTROL_ID_CODE_ES2_0:
 122                         *omap_si_rev = OMAP4430_ES2_0;
 123                         break;
 124                 case OMAP4_CONTROL_ID_CODE_ES2_1:
 125                         *omap_si_rev = OMAP4430_ES2_1;
 126                         break;
 127                 case OMAP4_CONTROL_ID_CODE_ES2_2:
 128                         *omap_si_rev = OMAP4430_ES2_2;
 129                         break;
 130                 default:
 131                         *omap_si_rev = OMAP4430_ES2_0;
 132                         break;
 133                 }
 134                 break;
 135         case MIDR_CORTEX_A9_R1P3:
 136                 *omap_si_rev = OMAP4430_ES2_3;
 137                 break;
 138         case MIDR_CORTEX_A9_R2P10:
 139                 switch (readl(CONTROL_ID_CODE)) {
 140                 case OMAP4470_CONTROL_ID_CODE_ES1_0:
 141                         *omap_si_rev = OMAP4470_ES1_0;
 142                         break;
 143                 case OMAP4460_CONTROL_ID_CODE_ES1_1:
 144                         *omap_si_rev = OMAP4460_ES1_1;
 145                         break;
 146                 case OMAP4460_CONTROL_ID_CODE_ES1_0:
 147                 default:
 148                         *omap_si_rev = OMAP4460_ES1_0;
 149                         break;
 150                 }
 151                 break;
 152         default:
 153                 *omap_si_rev = OMAP4430_SILICON_ID_INVALID;
 154                 break;
 155         }
 156 }
 157
 158 void omap_die_id(unsigned int *die_id)
 159 {
 160         die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
 161         die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
 162         die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
 163         die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
 164 }
 165
 166 #ifndef CONFIG_SYS_L2CACHE_OFF
 167 void v7_outer_cache_enable(void)
 168 {
 169         omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
 170 }
 171
 172 void v7_outer_cache_disable(void)
 173 {
 174         omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
 175 }
 176 #endif /* !CONFIG_SYS_L2CACHE_OFF */
 177
 178 void vmmc_pbias_config(uint voltage)
 179 {
 180         u32 value = 0;
 181
 182         value = readl((*ctrl)->control_pbiaslite);
 183         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
 184         writel(value, (*ctrl)->control_pbiaslite);
 185         value = readl((*ctrl)->control_pbiaslite);
 186         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 187         writel(value, (*ctrl)->control_pbiaslite);
 188 }