arch/arm/mach-omap2/omap4/boot.c

   1 /*
   2  * OMAP4 boot
   3  *
   4  * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/omap_common.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <spl.h>
  14
  15 static u32 boot_devices[] = {
  16         BOOT_DEVICE_MMC2,
  17         BOOT_DEVICE_XIP,
  18         BOOT_DEVICE_XIPWAIT,
  19         BOOT_DEVICE_NAND,
  20         BOOT_DEVICE_XIPWAIT,
  21         BOOT_DEVICE_MMC1,
  22         BOOT_DEVICE_ONENAND,
  23         BOOT_DEVICE_ONENAND,
  24         BOOT_DEVICE_MMC2,
  25         BOOT_DEVICE_ONENAND,
  26         BOOT_DEVICE_XIPWAIT,
  27         BOOT_DEVICE_NAND,
  28         BOOT_DEVICE_NAND,
  29         BOOT_DEVICE_MMC1,
  30         BOOT_DEVICE_ONENAND,
  31         BOOT_DEVICE_MMC2,
  32         BOOT_DEVICE_XIP,
  33         BOOT_DEVICE_XIPWAIT,
  34         BOOT_DEVICE_NAND,
  35         BOOT_DEVICE_MMC1,
  36         BOOT_DEVICE_MMC1,
  37         BOOT_DEVICE_ONENAND,
  38         BOOT_DEVICE_MMC2,
  39         BOOT_DEVICE_XIP,
  40         BOOT_DEVICE_MMC2_2,
  41         BOOT_DEVICE_NAND,
  42         BOOT_DEVICE_MMC2_2,
  43         BOOT_DEVICE_MMC1,
  44         BOOT_DEVICE_MMC2_2,
  45         BOOT_DEVICE_MMC2_2,
  46         BOOT_DEVICE_NONE,
  47         BOOT_DEVICE_XIPWAIT,
  48 };
  49
  50 u32 omap_sys_boot_device(void)
  51 {
  52         u32 sys_boot;
  53
  54         /* Grab the first 5 bits of the status register for SYS_BOOT. */
  55         sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1);
  56
  57         if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
  58                 return BOOT_DEVICE_NONE;
  59
  60         return boot_devices[sys_boot];
  61 }
  62
  63 int omap_reboot_mode(char *mode, unsigned int length)
  64 {
  65         unsigned int limit;
  66         unsigned int i;
  67
  68         if (length < 2)
  69                 return -1;
  70
  71         if (!warm_reset())
  72                 return -1;
  73
  74         limit = (length < OMAP_REBOOT_REASON_SIZE) ? length :
  75                 OMAP_REBOOT_REASON_SIZE;
  76
  77         for (i = 0; i < (limit - 1); i++)
  78                 mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE +
  79                         OMAP_REBOOT_REASON_OFFSET + i));
  80
  81         mode[i] = '\0';
  82
  83         return 0;
  84 }
  85
  86 int omap_reboot_mode_clear(void)
  87 {
  88         writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET));
  89
  90         return 0;
  91 }
  92
  93 int omap_reboot_mode_store(char *mode)
  94 {
  95         unsigned int i;
  96
  97         for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++)
  98                 writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE +
  99                         OMAP_REBOOT_REASON_OFFSET + i));
 100
 101         writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE +
 102                 OMAP_REBOOT_REASON_OFFSET + i));
 103
 104         return 0;
 105 }