1 // SPDX-License-Identifier: GPL-2.0+
3 * Functions related to OMAP3 SDRC.
5 * This file has been created after exctracting and consolidating
6 * the SDRC related content from mem.c and board.c, also created
7 * generic init function (mem_init).
9 * Copyright (C) 2004-2010
10 * Texas Instruments Incorporated - http://www.ti.com/
13 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
16 * Vaibhav Hiremath <hvaibhav@ti.com>
18 * Original implementation by (mem.c, board.c) :
19 * Sunil Kumar <sunilsaini05@gmail.com>
20 * Shashi Ranjan <shashiranjanmca05@gmail.com>
21 * Manikandan Pillai <mani.pillai@ti.com>
26 #include <asm/arch/mem.h>
27 #include <asm/arch/sys_proto.h>
29 DECLARE_GLOBAL_DATA_PTR;
30 extern omap3_sysinfo sysinfo;
32 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
36 * - Return 1 if mem type in use is SDR
40 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
46 * make_cs1_contiguous -
47 * - When we have CS1 populated we want to have it mapped after cs0 to allow
48 * command line mem=xyz use all memory with out discontinuous support
49 * compiled in. We could do it in the ATAG, but there really is two banks...
51 void make_cs1_contiguous(void)
53 u32 size, a_add_low, a_add_high;
55 size = get_sdr_cs_size(CS0);
56 size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
57 a_add_high = (size & 3) << 8; /* set up low field */
58 a_add_low = (size & 0x3C) >> 2; /* set up high field */
59 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
66 * - Get size of chip select 0/1
68 u32 get_sdr_cs_size(u32 cs)
72 /* get ram size field */
73 size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
74 size &= 0x3FF; /* remove unwanted bits */
75 size <<= 21; /* multiply by 2 MiB to find size in MB */
81 * - Get offset of cs from cs0 start
83 u32 get_sdr_cs_offset(u32 cs)
90 offset = readl(&sdrc_base->cs_cfg);
91 offset = (offset & 15) << 27 | (offset & 0x300) << 17;
97 * write_sdrc_timings -
98 * - Takes CS and associated timings and initalize SDRAM
99 * - Test CS to make sure it's OK for use
101 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
102 struct board_sdrc_timings *timings)
104 /* Setup timings we got from the board. */
105 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
106 writel(timings->ctrla, &sdrc_actim_base->ctrla);
107 writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
108 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
109 writel(CMD_NOP, &sdrc_base->cs[cs].manual);
110 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
111 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
112 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
113 writel(timings->mr, &sdrc_base->cs[cs].mr);
116 * Test ram in this bank
117 * Disable if bad or not present
120 writel(0, &sdrc_base->cs[cs].mcfg);
125 * - Code called once in C-Stack only context for CS0 and with early being
126 * true and a possible 2nd time depending on memory configuration from
127 * stack+global context.
129 void do_sdrc_init(u32 cs, u32 early)
131 struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
132 struct board_sdrc_timings timings;
134 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
135 sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
137 /* set some default timings */
138 timings.sharing = SDRC_SHARING;
141 * When called in the early context this may be SPL and we will
142 * need to set all of the timings. This ends up being board
143 * specific so we call a helper function to take care of this
144 * for us. Otherwise, to be safe, we need to copy the settings
145 * from the first bank to the second. We will setup CS0,
146 * then set cs_cfg to the appropriate value then try and
149 #ifdef CONFIG_SPL_BUILD
150 /* set/modify board-specific timings */
151 get_board_mem_timings(&timings);
154 /* reset sdrc controller */
155 writel(SOFTRESET, &sdrc_base->sysconfig);
156 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
158 writel(0, &sdrc_base->sysconfig);
160 /* setup sdrc to ball mux */
161 writel(timings.sharing, &sdrc_base->sharing);
163 /* Disable Power Down of CKE because of 1 CKE on combo part */
164 writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
167 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
169 #ifdef CONFIG_SPL_BUILD
170 write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
171 make_cs1_contiguous();
172 write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
178 * If we aren't using SPL we have been loaded by some
179 * other means which may not have correctly initialized
180 * both CS0 and CS1 (such as some older versions of x-loader)
181 * so we may be asked now to setup CS1.
184 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
185 timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
186 timings.ctrla = readl(&sdrc_actim_base0->ctrla);
187 timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
188 timings.mr = readl(&sdrc_base->cs[CS0].mr);
189 write_sdrc_timings(cs, sdrc_actim_base1, &timings);
195 * - Sets uboots idea of sdram size
199 unsigned int size0 = 0, size1 = 0;
201 size0 = get_sdr_cs_size(CS0);
203 * We always need to have cs_cfg point at where the second
204 * bank would be, if present. Failure to do so can lead to
205 * strange situations where memory isn't detected and
206 * configured correctly. CS0 will already have been setup
209 make_cs1_contiguous();
210 do_sdrc_init(CS1, NOT_EARLY);
211 size1 = get_sdr_cs_size(CS1);
213 gd->ram_size = size0 + size1;
218 int dram_init_banksize(void)
220 unsigned int size0 = 0, size1 = 0;
222 size0 = get_sdr_cs_size(CS0);
223 size1 = get_sdr_cs_size(CS1);
225 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
226 gd->bd->bi_dram[0].size = size0;
227 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
228 gd->bd->bi_dram[1].size = size1;
235 * - Init the sdrc chip,
236 * - Selects CS0 and CS1,
240 /* only init up first bank here */
241 do_sdrc_init(CS0, EARLY_INIT);