1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Board specific setup info
6 * Texas Instruments, <www.ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
14 #include <asm/arch/mem.h>
15 #include <asm/arch/clocks_omap3.h>
16 #include <linux/linkage.h>
19 * Funtion for making PPA HAL API calls in secure devices
24 /* TODO: Re-evaluate the comment at the end regarding armv5 vs armv7 */
25 ENTRY(do_omap3_emu_romcode_call)
26 PUSH {r4-r12, lr} @ Save all registers from ROM code!
27 MOV r12, r0 @ Copy the Secure Service ID in R12
28 MOV r3, r1 @ Copy the pointer to va_list in R3
29 MOV r1, #0 @ Process ID - 0
30 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
32 MOV r6, #0xFF @ Indicate new Task call
33 mcr p15, 0, r0, c7, c10, 4 @ DSB
34 mcr p15, 0, r0, c7, c10, 5 @ DMB
35 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
36 @ because we use -march=armv5
38 ENDPROC(do_omap3_emu_romcode_call)
40 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
41 /**************************************************************************
42 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
43 * R1 = SRAM destination address.
44 *************************************************************************/
46 /* Copy DPLL code into SRAM */
47 adr r0, go_to_speed /* copy from start of go_to_speed... */
48 adr r2, lowlevel_init /* ... up to start of low_level_init */
50 ldmia r0!, {r3 - r10} /* copy from source address [r0] */
51 stmia r1!, {r3 - r10} /* copy to target address [r1] */
52 cmp r0, r2 /* until source end address [r2] */
54 mov pc, lr /* back to caller */
57 /* ***************************************************************************
58 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
59 * -executed from SRAM.
60 * R0 = CM_CLKEN_PLL-bypass value
61 * R1 = CM_CLKSEL1_PLL-m, n, and divider values
62 * R2 = CM_CLKSEL_CORE-divider values
63 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
65 * Note: If core unlocks/relocks and SDRAM is running fast already it gets
66 * confused. A reset of the controller gets it back. Taking away its
67 * L3 when its not in self refresh seems bad for it. Normally, this
68 * code runs from flash before SDR is init so that should be ok.
69 ****************************************************************************/
73 /* move into fast relock bypass */
77 ldr r5, [r3] /* get status */
78 and r5, r5, #0x1 /* isolate core status */
79 cmp r5, #0x1 /* still locked? */
80 beq wait1 /* if lock, loop */
82 /* set new dpll dividers _after_ in bypass */
84 str r1, [r5] /* set m, n, m2 */
86 str r2, [r5] /* set l3/l4/.. dividers*/
87 ldr r5, pll_div_add3 /* wkup */
88 ldr r2, pll_div_val3 /* rsm val */
90 ldr r5, pll_div_add4 /* gfx */
93 ldr r5, pll_div_add5 /* emu */
97 /* now prepare GPMC (flash) for new dpll speed */
98 /* flash needs to be stable when we jump back to it */
99 ldr r5, flash_cfg3_addr
100 ldr r2, flash_cfg3_val
102 ldr r5, flash_cfg4_addr
103 ldr r2, flash_cfg4_val
105 ldr r5, flash_cfg5_addr
106 ldr r2, flash_cfg5_val
108 ldr r5, flash_cfg1_addr
110 orr r2, r2, #0x3 /* up gpmc divider */
113 /* lock DPLL3 and wait a bit */
114 orr r0, r0, #0x7 /* set up for lock mode */
115 str r0, [r4] /* lock */
116 nop /* ARM slow at this point working at sys_clk */
121 ldr r5, [r3] /* get status */
122 and r5, r5, #0x1 /* isolate core status */
123 cmp r5, #0x1 /* still locked? */
124 bne wait2 /* if lock, loop */
130 mov pc, lr /* back to caller, locked */
133 _go_to_speed: .word go_to_speed
135 /* these constants need to be close for PIC code */
136 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
138 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
140 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
142 .word STNOR_GPMC_CONFIG3
144 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
146 .word STNOR_GPMC_CONFIG4
148 .word STNOR_GPMC_CONFIG5
150 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
160 .word (WKUP_RSM << 1)
174 str ip, [sp] /* stash ip register */
175 mov ip, lr /* save link reg across call */
176 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
178 * No need to copy/exec the clock code - DPLL adjust already done
179 * in NAND/oneNAND Boot.
181 ldr r1, =SRAM_CLK_CODE
183 #endif /* NAND Boot */
184 mov lr, ip /* restore link reg */
185 ldr ip, [sp] /* restore save ip */
186 /* tail-call s_init to setup pll, mux, memory */
189 ENDPROC(lowlevel_init)
191 /* the literal pools origin */
197 .word LOW_LEVEL_SRAM_STACK
199 /* DPLL(1-4) PARAM TABLES */
202 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
203 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
204 * The values are defined for all possible sysclk and for ES1 and ES2.
210 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
212 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
214 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
218 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
220 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
222 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
226 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
228 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
230 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
234 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
236 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
238 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
242 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
244 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
246 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
249 .globl get_mpu_dpll_param
251 adr r0, mpu_dpll_param
257 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
259 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
261 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
265 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
267 .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
269 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
273 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
275 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
277 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
281 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
283 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
285 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
289 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
291 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
293 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
296 .globl get_iva_dpll_param
298 adr r0, iva_dpll_param
301 /* Core DPLL targets for L3 at 166 & L133 */
305 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
307 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
309 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
313 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
315 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
317 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
321 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
323 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
325 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
329 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
331 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
333 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
337 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
339 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
341 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
343 .globl get_core_dpll_param
345 adr r0, core_dpll_param
348 /* PER DPLL values are same for both ES1 and ES2 */
351 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
354 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
357 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
360 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
363 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
365 .globl get_per_dpll_param
367 adr r0, per_dpll_param
370 /* PER2 DPLL values */
373 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
376 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
379 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
382 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
385 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
387 .globl get_per2_dpll_param
389 adr r0, per2_dpll_param
393 * Tables for 36XX/37XX devices
433 /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
434 .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
435 .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
436 .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
437 .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
438 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
442 .word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
444 .word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
446 .word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
448 .word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
450 .word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
453 ENTRY(get_36x_mpu_dpll_param)
454 adr r0, mpu_36x_dpll_param
456 ENDPROC(get_36x_mpu_dpll_param)
458 ENTRY(get_36x_iva_dpll_param)
459 adr r0, iva_36x_dpll_param
461 ENDPROC(get_36x_iva_dpll_param)
463 ENTRY(get_36x_core_dpll_param)
464 adr r0, core_36x_dpll_param
466 ENDPROC(get_36x_core_dpll_param)
468 ENTRY(get_36x_per_dpll_param)
469 adr r0, per_36x_dpll_param
471 ENDPROC(get_36x_per_dpll_param)
473 ENTRY(get_36x_per2_dpll_param)
474 adr r0, per2_36x_dpll_param
476 ENDPROC(get_36x_per2_dpll_param)