1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Board specific setup info
6 * Texas Instruments, <www.ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
14 #include <asm/arch/mem.h>
15 #include <asm/arch/clocks_omap3.h>
16 #include <linux/linkage.h>
19 * Funtion for making PPA HAL API calls in secure devices
24 ENTRY(do_omap3_emu_romcode_call)
25 PUSH {r4-r12, lr} @ Save all registers from ROM code!
26 MOV r12, r0 @ Copy the Secure Service ID in R12
27 MOV r3, r1 @ Copy the pointer to va_list in R3
28 MOV r1, #0 @ Process ID - 0
29 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
31 MOV r6, #0xFF @ Indicate new Task call
32 mcr p15, 0, r0, c7, c10, 4 @ DSB
33 mcr p15, 0, r0, c7, c10, 5 @ DMB
34 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
35 @ because we use -march=armv5
37 ENDPROC(do_omap3_emu_romcode_call)
39 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
40 /**************************************************************************
41 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
42 * R1 = SRAM destination address.
43 *************************************************************************/
45 /* Copy DPLL code into SRAM */
46 adr r0, go_to_speed /* copy from start of go_to_speed... */
47 adr r2, lowlevel_init /* ... up to start of low_level_init */
49 ldmia r0!, {r3 - r10} /* copy from source address [r0] */
50 stmia r1!, {r3 - r10} /* copy to target address [r1] */
51 cmp r0, r2 /* until source end address [r2] */
53 mov pc, lr /* back to caller */
56 /* ***************************************************************************
57 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
58 * -executed from SRAM.
59 * R0 = CM_CLKEN_PLL-bypass value
60 * R1 = CM_CLKSEL1_PLL-m, n, and divider values
61 * R2 = CM_CLKSEL_CORE-divider values
62 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
64 * Note: If core unlocks/relocks and SDRAM is running fast already it gets
65 * confused. A reset of the controller gets it back. Taking away its
66 * L3 when its not in self refresh seems bad for it. Normally, this
67 * code runs from flash before SDR is init so that should be ok.
68 ****************************************************************************/
72 /* move into fast relock bypass */
76 ldr r5, [r3] /* get status */
77 and r5, r5, #0x1 /* isolate core status */
78 cmp r5, #0x1 /* still locked? */
79 beq wait1 /* if lock, loop */
81 /* set new dpll dividers _after_ in bypass */
83 str r1, [r5] /* set m, n, m2 */
85 str r2, [r5] /* set l3/l4/.. dividers*/
86 ldr r5, pll_div_add3 /* wkup */
87 ldr r2, pll_div_val3 /* rsm val */
89 ldr r5, pll_div_add4 /* gfx */
92 ldr r5, pll_div_add5 /* emu */
96 /* now prepare GPMC (flash) for new dpll speed */
97 /* flash needs to be stable when we jump back to it */
98 ldr r5, flash_cfg3_addr
99 ldr r2, flash_cfg3_val
101 ldr r5, flash_cfg4_addr
102 ldr r2, flash_cfg4_val
104 ldr r5, flash_cfg5_addr
105 ldr r2, flash_cfg5_val
107 ldr r5, flash_cfg1_addr
109 orr r2, r2, #0x3 /* up gpmc divider */
112 /* lock DPLL3 and wait a bit */
113 orr r0, r0, #0x7 /* set up for lock mode */
114 str r0, [r4] /* lock */
115 nop /* ARM slow at this point working at sys_clk */
120 ldr r5, [r3] /* get status */
121 and r5, r5, #0x1 /* isolate core status */
122 cmp r5, #0x1 /* still locked? */
123 bne wait2 /* if lock, loop */
129 mov pc, lr /* back to caller, locked */
132 _go_to_speed: .word go_to_speed
134 /* these constants need to be close for PIC code */
135 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
137 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
139 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
141 .word STNOR_GPMC_CONFIG3
143 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
145 .word STNOR_GPMC_CONFIG4
147 .word STNOR_GPMC_CONFIG5
149 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
159 .word (WKUP_RSM << 1)
173 str ip, [sp] /* stash ip register */
174 mov ip, lr /* save link reg across call */
175 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
177 * No need to copy/exec the clock code - DPLL adjust already done
178 * in NAND/oneNAND Boot.
180 ldr r1, =SRAM_CLK_CODE
182 #endif /* NAND Boot */
183 mov lr, ip /* restore link reg */
184 ldr ip, [sp] /* restore save ip */
185 /* tail-call s_init to setup pll, mux, memory */
188 ENDPROC(lowlevel_init)
190 /* the literal pools origin */
196 .word LOW_LEVEL_SRAM_STACK
198 /* DPLL(1-4) PARAM TABLES */
201 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
202 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
203 * The values are defined for all possible sysclk and for ES1 and ES2.
209 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
211 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
213 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
217 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
219 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
221 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
225 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
227 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
229 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
233 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
235 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
237 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
241 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
243 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
245 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
248 .globl get_mpu_dpll_param
250 adr r0, mpu_dpll_param
256 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
258 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
260 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
264 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
266 .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
268 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
272 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
274 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
276 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
280 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
282 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
284 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
288 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
290 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
292 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
295 .globl get_iva_dpll_param
297 adr r0, iva_dpll_param
300 /* Core DPLL targets for L3 at 166 & L133 */
304 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
306 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
308 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
312 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
314 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
316 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
320 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
322 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
324 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
328 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
330 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
332 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
336 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
338 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
340 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
342 .globl get_core_dpll_param
344 adr r0, core_dpll_param
347 /* PER DPLL values are same for both ES1 and ES2 */
350 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
353 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
356 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
359 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
362 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
364 .globl get_per_dpll_param
366 adr r0, per_dpll_param
369 /* PER2 DPLL values */
372 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
375 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
378 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
381 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
384 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
386 .globl get_per2_dpll_param
388 adr r0, per2_dpll_param
392 * Tables for 36XX/37XX devices
432 /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
433 .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
434 .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
435 .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
436 .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
437 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
441 .word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
443 .word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
445 .word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
447 .word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
449 .word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
452 ENTRY(get_36x_mpu_dpll_param)
453 adr r0, mpu_36x_dpll_param
455 ENDPROC(get_36x_mpu_dpll_param)
457 ENTRY(get_36x_iva_dpll_param)
458 adr r0, iva_36x_dpll_param
460 ENDPROC(get_36x_iva_dpll_param)
462 ENTRY(get_36x_core_dpll_param)
463 adr r0, core_36x_dpll_param
465 ENDPROC(get_36x_core_dpll_param)
467 ENTRY(get_36x_per_dpll_param)
468 adr r0, per_36x_dpll_param
470 ENDPROC(get_36x_per_dpll_param)
472 ENTRY(get_36x_per2_dpll_param)
473 adr r0, per2_36x_dpll_param
475 ENDPROC(get_36x_per2_dpll_param)