3 * Common board functions for OMAP3 based boards.
5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com>
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
17 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/mem.h>
25 #include <asm/cache.h>
26 #include <asm/armv7.h>
28 #include <asm/omap_common.h>
29 #include <linux/compiler.h>
31 DECLARE_GLOBAL_DATA_PTR;
34 extern omap3_sysinfo sysinfo;
35 #ifndef CONFIG_SYS_L2CACHE_OFF
36 static void omap3_invalidate_l2_cache_secure(void);
40 static const struct omap_gpio_platdata omap34xx_gpio[] = {
41 { 0, OMAP34XX_GPIO1_BASE },
42 { 1, OMAP34XX_GPIO2_BASE },
43 { 2, OMAP34XX_GPIO3_BASE },
44 { 3, OMAP34XX_GPIO4_BASE },
45 { 4, OMAP34XX_GPIO5_BASE },
46 { 5, OMAP34XX_GPIO6_BASE },
49 U_BOOT_DEVICES(omap34xx_gpios) = {
50 { "gpio_omap", &omap34xx_gpio[0] },
51 { "gpio_omap", &omap34xx_gpio[1] },
52 { "gpio_omap", &omap34xx_gpio[2] },
53 { "gpio_omap", &omap34xx_gpio[3] },
54 { "gpio_omap", &omap34xx_gpio[4] },
55 { "gpio_omap", &omap34xx_gpio[5] },
60 static const struct gpio_bank gpio_bank_34xx[6] = {
61 { (void *)OMAP34XX_GPIO1_BASE },
62 { (void *)OMAP34XX_GPIO2_BASE },
63 { (void *)OMAP34XX_GPIO3_BASE },
64 { (void *)OMAP34XX_GPIO4_BASE },
65 { (void *)OMAP34XX_GPIO5_BASE },
66 { (void *)OMAP34XX_GPIO6_BASE },
69 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
73 /******************************************************************************
74 * Routine: secure_unlock
75 * Description: Setup security registers for access
77 *****************************************************************************/
78 void secure_unlock_mem(void)
80 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
81 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
82 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
83 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
84 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
86 /* Protection Module Register Target APE (PM_RT) */
87 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
88 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
89 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
90 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
92 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
93 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
94 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
96 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
97 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
98 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
99 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
102 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
103 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
104 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
106 /* SDRC region 0 public */
107 writel(UNLOCK_1, &sms_base->rg_att0);
110 /******************************************************************************
111 * Routine: secureworld_exit()
112 * Description: If chip is EMU and boot type is external
113 * configure secure registers and exit secure world
115 *****************************************************************************/
116 void secureworld_exit(void)
120 /* configure non-secure access control register */
121 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
122 /* enabling co-processor CP10 and CP11 accesses in NS world */
123 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
125 * allow allocation of locked TLBs and L2 lines in NS world
126 * allow use of PLE registers in NS world also
128 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
129 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
131 /* Enable ASA in ACR register */
132 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
133 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
134 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
136 /* Exiting secure world */
137 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
138 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
139 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
142 /******************************************************************************
143 * Routine: try_unlock_sram()
144 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
146 *****************************************************************************/
147 void try_unlock_memory(void)
150 int in_sdram = is_running_in_sdram();
153 * if GP device unlock device SRAM for general use
154 * secure code breaks for Secure/Emulation device - HS/E/T
156 mode = get_device_type();
157 if (mode == GP_DEVICE)
161 * If device is EMU and boot is XIP external booting
162 * Unlock firewalls and disable L2 and put chip
163 * out of secure world
165 * Assuming memories are unlocked by the demon who put us in SDRAM
167 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
176 void early_system_init(void)
181 /******************************************************************************
183 * Description: Does early system init of muxing and clocks.
184 * - Called path is with SRAM stack.
185 *****************************************************************************/
193 #ifndef CONFIG_SYS_L2CACHE_OFF
194 /* Invalidate L2-cache from secure mode */
195 omap3_invalidate_l2_cache_secure();
205 #ifdef CONFIG_USB_EHCI_OMAP
206 ehci_clocks_enable();
210 #ifdef CONFIG_SPL_BUILD
211 void board_init_f(ulong dummy)
216 * Save the boot parameters passed from romcode.
217 * We cannot delay the saving further than this,
218 * to prevent overwrites.
220 save_omap_boot_params();
225 * Routine: misc_init_r
226 * Description: A basic misc_init_r that just displays the die ID
228 int __weak misc_init_r(void)
230 omap_die_id_display();
235 /******************************************************************************
236 * Routine: wait_for_command_complete
237 * Description: Wait for posting to finish on watchdog
238 *****************************************************************************/
239 static void wait_for_command_complete(struct watchdog *wd_base)
243 pending = readl(&wd_base->wwps);
247 /******************************************************************************
248 * Routine: watchdog_init
249 * Description: Shut down watch dogs
250 *****************************************************************************/
251 void watchdog_init(void)
253 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
254 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
257 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
258 * either taken care of by ROM (HS/EMU) or not accessible (GP).
259 * We need to take care of WD2-MPU or take a PRCM reset. WD3
260 * should not be running and does not generate a PRCM reset.
263 setbits_le32(&prcm_base->fclken_wkup, 0x20);
264 setbits_le32(&prcm_base->iclken_wkup, 0x20);
265 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
267 writel(WD_UNLOCK1, &wd2_base->wspr);
268 wait_for_command_complete(wd2_base);
269 writel(WD_UNLOCK2, &wd2_base->wspr);
272 /******************************************************************************
273 * Dummy function to handle errors for EABI incompatibility
274 *****************************************************************************/
279 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
280 /******************************************************************************
281 * OMAP3 specific command to switch between NAND HW and SW ecc
282 *****************************************************************************/
283 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
285 int hw, strength = 1;
287 if (argc < 2 || argc > 3)
290 if (strncmp(argv[1], "hw", 2) == 0) {
293 if (strncmp(argv[2], "bch8", 4) == 0)
295 else if (strncmp(argv[2], "bch16", 5) == 0)
297 else if (strncmp(argv[2], "hamming", 7) != 0)
300 } else if (strncmp(argv[1], "sw", 2) == 0) {
303 if (strncmp(argv[2], "bch8", 4) == 0)
305 else if (strncmp(argv[2], "hamming", 7) != 0)
312 return -omap_nand_switch_ecc(hw, strength);
315 printf ("Usage: nandecc %s\n", cmdtp->usage);
320 nandecc, 3, 1, do_switch_ecc,
321 "switch OMAP3 NAND ECC calculation algorithm",
322 "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
323 " and 8-bit/16-bit BCH\n"
324 " ecc calculation (second parameter may"
326 "nandecc sw - Switch to NAND software ecc algorithm."
329 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
331 #ifdef CONFIG_DISPLAY_BOARDINFO
333 * Print board information
335 int checkboard (void)
344 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
345 sysinfo.nand_string);
349 #endif /* CONFIG_DISPLAY_BOARDINFO */
351 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
353 u32 i, num_params = *parameters;
354 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
357 * copy the parameters to an un-cached area to avoid coherency
360 for (i = 0; i < num_params; i++) {
361 __raw_writel(*parameters, sram_scratch_space);
363 sram_scratch_space++;
366 /* Now make the PPA call */
367 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
370 void __weak omap3_set_aux_cr_secure(u32 acr)
372 struct emu_hal_params emu_romcode_params;
374 emu_romcode_params.num_params = 1;
375 emu_romcode_params.param1 = acr;
376 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
377 (u32 *)&emu_romcode_params);
380 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
381 u32 cpu_rev_comb, u32 cpu_variant,
384 if (get_device_type() == GP_DEVICE)
385 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
387 /* L2 Cache Auxiliary Control Register is not banked */
390 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
391 u32 cpu_variant, u32 cpu_rev)
393 /* Write ACR - affects secure banked bits */
394 if (get_device_type() == GP_DEVICE)
395 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
397 omap3_set_aux_cr_secure(acr);
399 /* Write ACR - affects non-secure banked bits - some erratas need it */
400 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
404 #ifndef CONFIG_SYS_L2CACHE_OFF
405 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
410 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
413 v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
417 /* Invalidate the entire L2 cache from secure mode */
418 static void omap3_invalidate_l2_cache_secure(void)
420 if (get_device_type() == GP_DEVICE) {
421 omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
423 struct emu_hal_params emu_romcode_params;
424 emu_romcode_params.num_params = 1;
425 emu_romcode_params.param1 = 0;
426 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
427 (u32 *)&emu_romcode_params);
431 void v7_outer_cache_enable(void)
436 * On some revisions L2EN bit is banked on some revisions it's not
437 * No harm in setting both banked bits(in fact this is required
440 omap3_update_aux_cr(0x2, 0);
443 void omap3_outer_cache_disable(void)
447 * On some revisions L2EN bit is banked on some revisions it's not
448 * No harm in clearing both banked bits(in fact this is required
451 omap3_update_aux_cr(0, 0x2);
453 #endif /* !CONFIG_SYS_L2CACHE_OFF */