1 // SPDX-License-Identifier: GPL-2.0+
4 * Common functions for OMAP4/5 based boards
7 * Texas Instruments, <www.ti.com>
10 * Aneesh V <aneesh@ti.com>
11 * Steve Sakoman <steve@sakoman.com>
15 #include <asm/cache.h>
17 DECLARE_GLOBAL_DATA_PTR;
20 * Without LPAE short descriptors are used
23 * The last 2 bits set to 0b10
27 * With LPAE cache configuration happens via MAIR0 register
28 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
29 * 0xFF maps to Cache writeback with Read and Write Allocate set
30 * The bits[1:0] should have the value 0b01 for the first level
35 #ifdef CONFIG_ARMV7_LPAE
36 #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
38 #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
41 #define ARMV7_DOMAIN_CLIENT 1
42 #define ARMV7_DOMAIN_MASK (0x3 << 0)
44 void enable_caches(void)
47 /* Enable I cache if not enabled */
54 void dram_bank_mmu_setup(int bank)
59 u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
60 u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
61 u32 end = start + size;
63 debug("%s: bank: %d\n", __func__, bank);
64 for (i = start; i < end; i++)
65 set_section_dcache(i, ARMV7_DCACHE_POLICY);
68 void arm_init_domains(void)
74 * Set DOMAIN to client access so that all permissions
75 * set in pagetables are validated by the mmu.
77 reg &= ~ARMV7_DOMAIN_MASK;
78 reg |= ARMV7_DOMAIN_CLIENT;