1 // SPDX-License-Identifier: GPL-2.0+
4 * Common functions for OMAP4/5 based boards
7 * Texas Instruments, <www.ti.com>
10 * Aneesh V <aneesh@ti.com>
11 * Steve Sakoman <steve@sakoman.com>
16 #include <asm/cache.h>
18 DECLARE_GLOBAL_DATA_PTR;
21 * Without LPAE short descriptors are used
24 * The last 2 bits set to 0b10
28 * With LPAE cache configuration happens via MAIR0 register
29 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
30 * 0xFF maps to Cache writeback with Read and Write Allocate set
31 * The bits[1:0] should have the value 0b01 for the first level
36 #ifdef CONFIG_ARMV7_LPAE
37 #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
39 #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
42 #define ARMV7_DOMAIN_CLIENT 1
43 #define ARMV7_DOMAIN_MASK (0x3 << 0)
45 void enable_caches(void)
48 /* Enable I cache if not enabled */
55 void dram_bank_mmu_setup(int bank)
60 u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
61 u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
62 u32 end = start + size;
64 debug("%s: bank: %d\n", __func__, bank);
65 for (i = start; i < end; i++)
66 set_section_dcache(i, ARMV7_DCACHE_POLICY);
69 void arm_init_domains(void)
75 * Set DOMAIN to client access so that all permissions
76 * set in pagetables are validated by the mmu.
78 reg &= ~ARMV7_DOMAIN_MASK;
79 reg |= ARMV7_DOMAIN_CLIENT;