1 // SPDX-License-Identifier: GPL-2.0+
4 * Texas Instruments, <www.ti.com>
7 * Mansoor Ahamed <mansoor.ahamed@ti.com>
10 * Manikandan Pillai <mani.pillai@ti.com>
11 * Richard Woodruff <r-woodruff2@ti.com>
12 * Syed Mohammed Khasim <khasim@ti.com>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/mem.h>
19 #include <asm/arch/sys_proto.h>
21 #include <linux/mtd/omap_gpmc.h>
22 #include <jffs2/load_kernel.h>
24 const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
26 #if defined(CONFIG_NOR)
27 char gpmc_cs0_flash = MTD_DEV_TYPE_NOR;
28 #elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
29 char gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
30 #elif defined(CONFIG_CMD_ONENAND)
31 char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
33 char gpmc_cs0_flash = -1;
36 #if defined(CONFIG_OMAP34XX)
37 /********************************************************
38 * mem_ok() - test used to see if timings are correct
39 * for a part. Helps in guessing which part
40 * we are currently using.
41 *******************************************************/
45 u32 pattern = 0x12345678;
47 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
49 writel(0x0, addr + 0x400); /* clear pos A */
50 writel(pattern, addr); /* pattern to pos B */
51 writel(0x0, addr + 4); /* remove pattern off the bus */
52 val1 = readl(addr + 0x400); /* get pos A value */
53 val2 = readl(addr); /* get val2 */
54 writel(0x0, addr + 0x400); /* clear pos A */
56 if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
63 void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
66 writel(0, &cs->config7);
68 /* Delay for settling */
69 writel(gpmc_config[0], &cs->config1);
70 writel(gpmc_config[1], &cs->config2);
71 writel(gpmc_config[2], &cs->config3);
72 writel(gpmc_config[3], &cs->config4);
73 writel(gpmc_config[4], &cs->config5);
74 writel(gpmc_config[5], &cs->config6);
75 /* Enable the config */
76 writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
77 (1 << 6)), &cs->config7);
81 void set_gpmc_cs0(int flash_type)
85 #if defined(CONFIG_NOR)
86 const u32 gpmc_regs_nor[GPMC_MAX_REG] = {
96 #if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
97 const u32 gpmc_regs_nand[GPMC_MAX_REG] = {
107 #if defined(CONFIG_CMD_ONENAND)
108 const u32 gpmc_regs_onenand[GPMC_MAX_REG] = {
109 ONENAND_GPMC_CONFIG1,
110 ONENAND_GPMC_CONFIG2,
111 ONENAND_GPMC_CONFIG3,
112 ONENAND_GPMC_CONFIG4,
113 ONENAND_GPMC_CONFIG5,
114 ONENAND_GPMC_CONFIG6,
119 switch (flash_type) {
120 #if defined(CONFIG_NOR)
121 case MTD_DEV_TYPE_NOR:
122 gpmc_regs = gpmc_regs_nor;
123 base = CONFIG_SYS_FLASH_BASE;
124 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
125 ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
126 ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
127 ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
131 #if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
132 case MTD_DEV_TYPE_NAND:
133 gpmc_regs = gpmc_regs_nand;
134 base = CONFIG_SYS_NAND_BASE;
135 size = GPMC_SIZE_16M;
138 #if defined(CONFIG_CMD_ONENAND)
139 case MTD_DEV_TYPE_ONENAND:
140 gpmc_regs = gpmc_regs_onenand;
141 base = CONFIG_SYS_ONENAND_BASE;
142 size = GPMC_SIZE_128M;
146 /* disable the GPMC0 config set by ROM code */
147 writel(0, &gpmc_cfg->cs[0].config7);
152 /* enable chip-select specific configurations */
153 enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
156 /*****************************************************
157 * gpmc_init(): init gpmc bus
158 * Init GPMC for x16, MuxMode (SDRAM in x32).
159 * This code can only be executed from SRAM or SDRAM.
160 *****************************************************/
163 /* global settings */
164 writel(0x00000008, &gpmc_cfg->sysconfig);
165 writel(0x00000000, &gpmc_cfg->irqstatus);
166 writel(0x00000000, &gpmc_cfg->irqenable);
167 /* disable timeout, set a safe reset value */
168 writel(0x00001ff0, &gpmc_cfg->timeout_control);
169 writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ?
170 0x00000200 : 0x00000012, &gpmc_cfg->config);
172 set_gpmc_cs0(gpmc_cs0_flash);