2 * OMAP2/3 System Control Module register access
4 * Copyright (C) 2007 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
7 * Written by Paul Walmsley
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
18 #include <plat/common.h>
19 #include <plat/sdrc.h>
21 #include "cm-regbits-34xx.h"
22 #include "prm-regbits-34xx.h"
23 #include "prm2xxx_3xxx.h"
24 #include "cm2xxx_3xxx.h"
29 /* Used by omap3_ctrl_save_padconf() */
30 #define START_PADCONF_SAVE 0x2
31 #define PADCONF_SAVE_DONE 0x1
33 static void __iomem *omap2_ctrl_base;
34 static void __iomem *omap4_ctrl_pad_base;
36 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
37 struct omap3_scratchpad {
39 u32 public_restore_ptr;
40 u32 secure_ram_restore_ptr;
41 u32 sdrc_module_semaphore;
42 u32 prcm_block_offset;
43 u32 sdrc_block_offset;
46 struct omap3_scratchpad_prcm_block {
57 u32 cm_autoidle_pll_mpu;
58 u32 cm_clksel1_pll_mpu;
59 u32 cm_clksel2_pll_mpu;
63 struct omap3_scratchpad_sdrc_block {
95 void *omap3_secure_ram_storage;
98 * This is used to store ARM registers in SDRAM before attempting
99 * an MPU OFF. The save and restore happens from the SRAM sleep code.
100 * The address is stored in scratchpad, so that it can be used
101 * during the restore path.
103 u32 omap3_arm_context[128];
105 struct omap3_control_regs {
132 u32 dss_dpll_spreading;
133 u32 core_dpll_spreading;
134 u32 per_dpll_spreading;
135 u32 usbhost_dpll_spreading;
141 u32 padconf_sys_nirq;
144 static struct omap3_control_regs control_context;
145 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
147 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
148 #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
150 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
152 if (omap2_globals->ctrl)
153 omap2_ctrl_base = omap2_globals->ctrl;
155 if (omap2_globals->ctrl_pad)
156 omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
159 void __iomem *omap_ctrl_base_get(void)
161 return omap2_ctrl_base;
164 u8 omap_ctrl_readb(u16 offset)
166 return __raw_readb(OMAP_CTRL_REGADDR(offset));
169 u16 omap_ctrl_readw(u16 offset)
171 return __raw_readw(OMAP_CTRL_REGADDR(offset));
174 u32 omap_ctrl_readl(u16 offset)
176 return __raw_readl(OMAP_CTRL_REGADDR(offset));
179 void omap_ctrl_writeb(u8 val, u16 offset)
181 __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
184 void omap_ctrl_writew(u16 val, u16 offset)
186 __raw_writew(val, OMAP_CTRL_REGADDR(offset));
189 void omap_ctrl_writel(u32 val, u16 offset)
191 __raw_writel(val, OMAP_CTRL_REGADDR(offset));
195 * On OMAP4 control pad are not addressable from control
196 * core base. So the common omap_ctrl_read/write APIs breaks
197 * Hence export separate APIs to manage the omap4 pad control
198 * registers. This APIs will work only for OMAP4
201 u32 omap4_ctrl_pad_readl(u16 offset)
203 return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
206 void omap4_ctrl_pad_writel(u32 val, u16 offset)
208 __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
211 #ifdef CONFIG_ARCH_OMAP3
214 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
215 * @bootmode: 8-bit value to pass to some boot code
217 * Set the bootmode in the scratchpad RAM. This is used after the
218 * system restarts. Not sure what actually uses this - it may be the
219 * bootloader, rather than the boot ROM - contrary to the preserved
220 * comment below. No return value.
222 void omap3_ctrl_write_boot_mode(u8 bootmode)
226 l = ('B' << 24) | ('M' << 16) | bootmode;
229 * Reserve the first word in scratchpad for communicating
230 * with the boot ROM. A pointer to a data structure
231 * describing the boot process can be stored there,
232 * cf. OMAP34xx TRM, Initialization / Software Booting
235 * XXX This should use some omap_ctrl_writel()-type function
237 __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
242 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
244 * Clears the scratchpad contents in case of cold boot-
245 * called during bootup
247 void omap3_clear_scratchpad_contents(void)
249 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
250 void __iomem *v_addr;
252 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
253 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
254 OMAP3430_GLOBAL_COLD_RST_MASK) {
255 for ( ; offset <= max_offset; offset += 0x4)
256 __raw_writel(0x0, (v_addr + offset));
257 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
259 OMAP3_PRM_RSTST_OFFSET);
263 /* Populate the scratchpad structure with restore structure */
264 void omap3_save_scratchpad_contents(void)
266 void __iomem *scratchpad_address;
267 u32 arm_context_addr;
268 struct omap3_scratchpad scratchpad_contents;
269 struct omap3_scratchpad_prcm_block prcm_block_contents;
270 struct omap3_scratchpad_sdrc_block sdrc_block_contents;
273 * Populate the Scratchpad contents
275 * The "get_*restore_pointer" functions are used to provide a
276 * physical restore address where the ROM code jumps while waking
277 * up from MPU OFF/OSWR state.
278 * The restore pointer is stored into the scratchpad.
280 scratchpad_contents.boot_config_ptr = 0x0;
281 if (cpu_is_omap3630())
282 scratchpad_contents.public_restore_ptr =
283 virt_to_phys(omap3_restore_3630);
284 else if (omap_rev() != OMAP3430_REV_ES3_0 &&
285 omap_rev() != OMAP3430_REV_ES3_1 &&
286 omap_rev() != OMAP3430_REV_ES3_1_2)
287 scratchpad_contents.public_restore_ptr =
288 virt_to_phys(omap3_restore);
290 scratchpad_contents.public_restore_ptr =
291 virt_to_phys(omap3_restore_es3);
293 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
294 scratchpad_contents.secure_ram_restore_ptr = 0x0;
296 scratchpad_contents.secure_ram_restore_ptr =
297 (u32) __pa(omap3_secure_ram_storage);
298 scratchpad_contents.sdrc_module_semaphore = 0x0;
299 scratchpad_contents.prcm_block_offset = 0x2C;
300 scratchpad_contents.sdrc_block_offset = 0x64;
302 /* Populate the PRCM block contents */
303 prcm_block_contents.prm_clksrc_ctrl =
304 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
305 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
306 prcm_block_contents.prm_clksel =
307 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
308 OMAP3_PRM_CLKSEL_OFFSET);
309 prcm_block_contents.cm_clksel_core =
310 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
311 prcm_block_contents.cm_clksel_wkup =
312 omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
313 prcm_block_contents.cm_clken_pll =
314 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
316 * As per erratum i671, ROM code does not respect the PER DPLL
317 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
318 * Then, in anycase, clear these bits to avoid extra latencies.
320 prcm_block_contents.cm_autoidle_pll =
321 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
322 ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
323 prcm_block_contents.cm_clksel1_pll =
324 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
325 prcm_block_contents.cm_clksel2_pll =
326 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
327 prcm_block_contents.cm_clksel3_pll =
328 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
329 prcm_block_contents.cm_clken_pll_mpu =
330 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
331 prcm_block_contents.cm_autoidle_pll_mpu =
332 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
333 prcm_block_contents.cm_clksel1_pll_mpu =
334 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
335 prcm_block_contents.cm_clksel2_pll_mpu =
336 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
337 prcm_block_contents.prcm_block_size = 0x0;
339 /* Populate the SDRC block contents */
340 sdrc_block_contents.sysconfig =
341 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
342 sdrc_block_contents.cs_cfg =
343 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
344 sdrc_block_contents.sharing =
345 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
346 sdrc_block_contents.err_type =
347 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
348 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
349 sdrc_block_contents.dll_b_ctrl = 0x0;
351 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
352 * be programed to issue automatic self refresh on timeout
353 * of AUTO_CNT = 1 prior to any transition to OFF mode.
355 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
356 && (omap_rev() >= OMAP3430_REV_ES3_0))
357 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
358 ~(SDRC_POWER_AUTOCOUNT_MASK|
359 SDRC_POWER_CLKCTRL_MASK)) |
360 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
361 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
363 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
365 sdrc_block_contents.cs_0 = 0x0;
366 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
367 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
368 sdrc_block_contents.emr_1_0 = 0x0;
369 sdrc_block_contents.emr_2_0 = 0x0;
370 sdrc_block_contents.emr_3_0 = 0x0;
371 sdrc_block_contents.actim_ctrla_0 =
372 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
373 sdrc_block_contents.actim_ctrlb_0 =
374 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
375 sdrc_block_contents.rfr_ctrl_0 =
376 sdrc_read_reg(SDRC_RFR_CTRL_0);
377 sdrc_block_contents.cs_1 = 0x0;
378 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
379 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
380 sdrc_block_contents.emr_1_1 = 0x0;
381 sdrc_block_contents.emr_2_1 = 0x0;
382 sdrc_block_contents.emr_3_1 = 0x0;
383 sdrc_block_contents.actim_ctrla_1 =
384 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
385 sdrc_block_contents.actim_ctrlb_1 =
386 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
387 sdrc_block_contents.rfr_ctrl_1 =
388 sdrc_read_reg(SDRC_RFR_CTRL_1);
389 sdrc_block_contents.dcdl_1_ctrl = 0x0;
390 sdrc_block_contents.dcdl_2_ctrl = 0x0;
391 sdrc_block_contents.flags = 0x0;
392 sdrc_block_contents.block_size = 0x0;
394 arm_context_addr = virt_to_phys(omap3_arm_context);
396 /* Copy all the contents to the scratchpad location */
397 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
398 memcpy_toio(scratchpad_address, &scratchpad_contents,
399 sizeof(scratchpad_contents));
400 /* Scratchpad contents being 32 bits, a divide by 4 done here */
401 memcpy_toio(scratchpad_address +
402 scratchpad_contents.prcm_block_offset,
403 &prcm_block_contents, sizeof(prcm_block_contents));
404 memcpy_toio(scratchpad_address +
405 scratchpad_contents.sdrc_block_offset,
406 &sdrc_block_contents, sizeof(sdrc_block_contents));
408 * Copies the address of the location in SDRAM where ARM
409 * registers get saved during a MPU OFF transition.
411 memcpy_toio(scratchpad_address +
412 scratchpad_contents.sdrc_block_offset +
413 sizeof(sdrc_block_contents), &arm_context_addr, 4);
416 void omap3_control_save_context(void)
418 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
419 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
420 control_context.mem_dftrw0 =
421 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
422 control_context.mem_dftrw1 =
423 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
424 control_context.msuspendmux_0 =
425 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
426 control_context.msuspendmux_1 =
427 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
428 control_context.msuspendmux_2 =
429 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
430 control_context.msuspendmux_3 =
431 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
432 control_context.msuspendmux_4 =
433 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
434 control_context.msuspendmux_5 =
435 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
436 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
437 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
438 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
439 control_context.iva2_bootaddr =
440 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
441 control_context.iva2_bootmod =
442 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
443 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
444 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
445 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
446 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
447 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
448 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
449 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
450 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
451 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
452 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
453 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
454 control_context.dss_dpll_spreading =
455 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
456 control_context.core_dpll_spreading =
457 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
458 control_context.per_dpll_spreading =
459 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
460 control_context.usbhost_dpll_spreading =
461 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
462 control_context.pbias_lite =
463 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
464 control_context.temp_sensor =
465 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
466 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
467 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
468 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
469 control_context.padconf_sys_nirq =
470 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
474 void omap3_control_restore_context(void)
476 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
477 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
478 omap_ctrl_writel(control_context.mem_dftrw0,
479 OMAP343X_CONTROL_MEM_DFTRW0);
480 omap_ctrl_writel(control_context.mem_dftrw1,
481 OMAP343X_CONTROL_MEM_DFTRW1);
482 omap_ctrl_writel(control_context.msuspendmux_0,
483 OMAP2_CONTROL_MSUSPENDMUX_0);
484 omap_ctrl_writel(control_context.msuspendmux_1,
485 OMAP2_CONTROL_MSUSPENDMUX_1);
486 omap_ctrl_writel(control_context.msuspendmux_2,
487 OMAP2_CONTROL_MSUSPENDMUX_2);
488 omap_ctrl_writel(control_context.msuspendmux_3,
489 OMAP2_CONTROL_MSUSPENDMUX_3);
490 omap_ctrl_writel(control_context.msuspendmux_4,
491 OMAP2_CONTROL_MSUSPENDMUX_4);
492 omap_ctrl_writel(control_context.msuspendmux_5,
493 OMAP2_CONTROL_MSUSPENDMUX_5);
494 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
495 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
496 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
497 omap_ctrl_writel(control_context.iva2_bootaddr,
498 OMAP343X_CONTROL_IVA2_BOOTADDR);
499 omap_ctrl_writel(control_context.iva2_bootmod,
500 OMAP343X_CONTROL_IVA2_BOOTMOD);
501 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
502 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
503 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
504 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
505 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
506 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
507 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
508 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
509 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
510 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
511 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
512 omap_ctrl_writel(control_context.dss_dpll_spreading,
513 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
514 omap_ctrl_writel(control_context.core_dpll_spreading,
515 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
516 omap_ctrl_writel(control_context.per_dpll_spreading,
517 OMAP343X_CONTROL_PER_DPLL_SPREADING);
518 omap_ctrl_writel(control_context.usbhost_dpll_spreading,
519 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
520 omap_ctrl_writel(control_context.pbias_lite,
521 OMAP343X_CONTROL_PBIAS_LITE);
522 omap_ctrl_writel(control_context.temp_sensor,
523 OMAP343X_CONTROL_TEMP_SENSOR);
524 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
525 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
526 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
527 omap_ctrl_writel(control_context.padconf_sys_nirq,
528 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
532 void omap3630_ctrl_disable_rta(void)
534 if (!cpu_is_omap3630())
536 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
540 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
542 * Tell the SCM to start saving the padconf registers, then wait for
543 * the process to complete. Returns 0 unconditionally, although it
544 * should also eventually be able to return -ETIMEDOUT, if the save
547 * XXX This function is missing a timeout. What should it be?
549 int omap3_ctrl_save_padconf(void)
553 /* Save the padconf registers */
554 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
555 cpo |= START_PADCONF_SAVE;
556 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
558 /* wait for the save to complete */
559 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
560 & PADCONF_SAVE_DONE))
566 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */