1 // SPDX-License-Identifier: GPL-2.0+
4 * Clock initialization for OMAP4
7 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
11 * Based on previous work by:
12 * Santosh Shilimkar <santosh.shilimkar@ti.com>
13 * Rajendra Nayak <rnayak@ti.com>
17 #include <asm/omap_common.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/utils.h>
22 #include <asm/omap_gpio.h>
25 #ifndef CONFIG_SPL_BUILD
27 * printing to console doesn't work unless
28 * this code is executed from SPL
30 #define printf(fmt, args...)
34 const u32 sys_clk_array[8] = {
35 12000000, /* 12 MHz */
36 20000000, /* 20 MHz */
37 16800000, /* 16.8 MHz */
38 19200000, /* 19.2 MHz */
39 26000000, /* 26 MHz */
40 27000000, /* 27 MHz */
41 38400000, /* 38.4 MHz */
44 static inline u32 __get_sys_clk_index(void)
48 * For ES1 the ROM code calibration of sys clock is not reliable
49 * due to hw issue. So, use hard-coded value. If this value is not
50 * correct for any board over-ride this function in board file
51 * From ES2.0 onwards you will get this information from
54 if (omap_revision() == OMAP4430_ES1_0)
55 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
57 /* SYS_CLKSEL - 1 to match the dpll param array indices */
58 ind = (readl((*prcm)->cm_sys_clksel) &
59 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
64 u32 get_sys_clk_index(void)
65 __attribute__ ((weak, alias("__get_sys_clk_index")));
67 u32 get_sys_clk_freq(void)
69 u8 index = get_sys_clk_index();
70 return sys_clk_array[index];
73 void setup_post_dividers(u32 const base, const struct dpll_params *params)
75 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
77 /* Setup post-dividers */
79 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
81 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
82 if (params->m4_h11 >= 0)
83 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
84 if (params->m5_h12 >= 0)
85 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
86 if (params->m6_h13 >= 0)
87 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
88 if (params->m7_h14 >= 0)
89 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
91 writel(params->h21, &dpll_regs->cm_div_h21_dpll);
93 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
95 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
97 writel(params->h24, &dpll_regs->cm_div_h24_dpll);
100 static inline void do_bypass_dpll(u32 const base)
102 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
104 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
105 CM_CLKMODE_DPLL_DPLL_EN_MASK,
106 DPLL_EN_FAST_RELOCK_BYPASS <<
107 CM_CLKMODE_DPLL_EN_SHIFT);
110 static inline void wait_for_bypass(u32 const base)
112 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
114 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
116 printf("Bypassing DPLL failed %x\n", base);
120 static inline void do_lock_dpll(u32 const base)
122 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
124 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
125 CM_CLKMODE_DPLL_DPLL_EN_MASK,
126 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
129 static inline void wait_for_lock(u32 const base)
131 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
133 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
134 &dpll_regs->cm_idlest_dpll, LDELAY)) {
135 printf("DPLL locking failed for %x\n", base);
140 inline u32 check_for_lock(u32 const base)
142 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
143 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
148 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
150 u32 sysclk_ind = get_sys_clk_index();
151 return &dpll_data->mpu[sysclk_ind];
154 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
156 u32 sysclk_ind = get_sys_clk_index();
157 return &dpll_data->core[sysclk_ind];
160 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
162 u32 sysclk_ind = get_sys_clk_index();
163 return &dpll_data->per[sysclk_ind];
166 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
168 u32 sysclk_ind = get_sys_clk_index();
169 return &dpll_data->iva[sysclk_ind];
172 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
174 u32 sysclk_ind = get_sys_clk_index();
175 return &dpll_data->usb[sysclk_ind];
178 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
180 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
181 u32 sysclk_ind = get_sys_clk_index();
182 return &dpll_data->abe[sysclk_ind];
184 return dpll_data->abe;
188 static const struct dpll_params *get_ddr_dpll_params
189 (struct dplls const *dpll_data)
191 u32 sysclk_ind = get_sys_clk_index();
195 return &dpll_data->ddr[sysclk_ind];
198 #ifdef CONFIG_DRIVER_TI_CPSW
199 static const struct dpll_params *get_gmac_dpll_params
200 (struct dplls const *dpll_data)
202 u32 sysclk_ind = get_sys_clk_index();
204 if (!dpll_data->gmac)
206 return &dpll_data->gmac[sysclk_ind];
210 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
214 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
219 temp = readl(&dpll_regs->cm_clksel_dpll);
221 if (check_for_lock(base)) {
223 * The Dpll has already been locked by rom code using CH.
224 * Check if M,N are matching with Ideal nominal opp values.
225 * If matches, skip the rest otherwise relock.
227 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
228 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
229 if ((M != (params->m)) || (N != (params->n))) {
230 debug("\n %s Dpll locked, but not for ideal M = %d,"
231 "N = %d values, current values are M = %d,"
232 "N= %d" , dpll, params->m, params->n,
235 /* Dpll locked with ideal values for nominal opps. */
236 debug("\n %s Dpll already locked with ideal"
237 "nominal opp values", dpll);
240 goto setup_post_dividers;
247 temp &= ~CM_CLKSEL_DPLL_M_MASK;
248 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
250 temp &= ~CM_CLKSEL_DPLL_N_MASK;
251 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
253 writel(temp, &dpll_regs->cm_clksel_dpll);
256 setup_post_dividers(base, params);
262 /* Wait till the DPLL locks */
267 u32 omap_ddr_clk(void)
269 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
270 const struct dpll_params *core_dpll_params;
272 omap_rev = omap_revision();
273 sys_clk_khz = get_sys_clk_freq() / 1000;
275 core_dpll_params = get_core_dpll_params(*dplls_data);
277 debug("sys_clk %d\n ", sys_clk_khz * 1000);
279 /* Find Core DPLL locked frequency first */
280 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
281 (core_dpll_params->n + 1);
283 if (omap_rev < OMAP5430_ES1_0) {
285 * DDR frequency is PHY_ROOT_CLK/2
286 * PHY_ROOT_CLK = Fdpll/2/M2
291 * DDR frequency is PHY_ROOT_CLK
292 * PHY_ROOT_CLK = Fdpll/2/M2
297 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
298 ddr_clk *= 1000; /* convert to Hz */
299 debug("ddr_clk %d\n ", ddr_clk);
307 * Resulting MPU frequencies:
308 * 4430 ES1.0 : 600 MHz
309 * 4430 ES2.x : 792 MHz (OPP Turbo)
310 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
312 void configure_mpu_dpll(void)
314 const struct dpll_params *params;
315 struct dpll_regs *mpu_dpll_regs;
317 omap_rev = omap_revision();
320 * DCC and clock divider settings for 4460.
321 * DCC is required, if more than a certain frequency is required.
325 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
327 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
328 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
329 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
330 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
331 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
332 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
333 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
334 CM_CLKSEL_DCC_EN_MASK);
337 params = get_mpu_dpll_params(*dplls_data);
339 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
340 debug("MPU DPLL locked\n");
343 #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
344 defined(CONFIG_USB_MUSB_OMAP2PLUS)
345 static void setup_usb_dpll(void)
347 const struct dpll_params *params;
348 u32 sys_clk_khz, sd_div, num, den;
350 sys_clk_khz = get_sys_clk_freq() / 1000;
353 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
354 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
355 * - where CLKINP is sys_clk in MHz
356 * Use CLKINP in KHz and adjust the denominator accordingly so
357 * that we have enough accuracy and at the same time no overflow
359 params = get_usb_dpll_params(*dplls_data);
360 num = params->m * sys_clk_khz;
361 den = (params->n + 1) * 250 * 1000;
364 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
365 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
366 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
368 /* Now setup the dpll with the regular function */
369 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
373 static void setup_dplls(void)
376 const struct dpll_params *params;
377 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
379 debug("setup_dplls\n");
382 params = get_core_dpll_params(*dplls_data); /* default - safest */
384 * Do not lock the core DPLL now. Just set it up.
385 * Core DPLL will be locked after setting up EMIF
386 * using the FREQ_UPDATE method(freq_update_core())
388 if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
389 EMIF_SDRAM_TYPE_LPDDR2)
390 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
391 DPLL_NO_LOCK, "core");
393 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
395 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
396 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
397 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
398 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
399 writel(temp, (*prcm)->cm_clksel_core);
400 debug("Core DPLL configured\n");
403 params = get_per_dpll_params(*dplls_data);
404 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
405 params, DPLL_LOCK, "per");
406 debug("PER DPLL locked\n");
409 configure_mpu_dpll();
411 #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
412 defined(CONFIG_USB_MUSB_OMAP2PLUS)
415 params = get_ddr_dpll_params(*dplls_data);
416 do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
417 params, DPLL_LOCK, "ddr");
419 #ifdef CONFIG_DRIVER_TI_CPSW
420 params = get_gmac_dpll_params(*dplls_data);
421 do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
426 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
430 volt_offset -= pmic->base_offset;
432 offset_code = (volt_offset + pmic->step - 1) / pmic->step;
435 * Offset codes 1-6 all give the base voltage in Palmas
436 * Offset code 0 switches OFF the SMPS
438 return offset_code + pmic->start_code;
441 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
444 u32 offset = volt_mv;
450 pmic->pmic_bus_init();
451 /* See if we can first get the GPIO if needed */
453 ret = gpio_request(pmic->gpio, "PMIC_GPIO");
456 printf("%s: gpio %d request failed %d\n", __func__,
461 /* Pull the GPIO low to select SET0 register, while we program SET1 */
463 gpio_direction_output(pmic->gpio, 0);
465 /* convert to uV for better accuracy in the calculations */
468 offset_code = get_offset_code(offset, pmic);
470 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
473 if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
474 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
476 gpio_direction_output(pmic->gpio, 1);
479 int __weak get_voltrail_opp(int rail_offset)
482 * By default return OPP_NOM for all voltage rails.
487 static u32 optimize_vcore_voltage(struct volts const *v, int opp)
493 if (!v->efuse.reg[opp])
494 return v->value[opp];
496 switch (v->efuse.reg_bits) {
498 val = readw(v->efuse.reg[opp]);
501 val = readl(v->efuse.reg[opp]);
504 printf("Error: efuse 0x%08x bits=%d unknown\n",
505 v->efuse.reg[opp], v->efuse.reg_bits);
506 return v->value[opp];
510 printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
511 v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp]);
512 return v->value[opp];
515 debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
516 __func__, v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp],
521 #ifdef CONFIG_IODELAY_RECALIBRATION
522 void __weak recalibrate_iodelay(void)
528 * Setup the voltages for the main SoC core power domains.
529 * We start with the maximum voltages allowed here, as set in the corresponding
530 * vcores_data struct, and then scale (usually down) to the fused values that
531 * are retrieved from the SoC. The scaling happens only if the efuse.reg fields
533 * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
534 * compiled conditionally. Note that the new code writes the scaled (or zeroed)
535 * values back to the vcores_data struct for eventual reuse. Zero values mean
536 * that the corresponding rails are not controlled separately, and are not sent
539 void scale_vcores(struct vcores_data const *vcores)
542 struct volts *pv = (struct volts *)vcores;
545 for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
546 opp = get_voltrail_opp(i);
547 debug("%d -> ", pv->value[opp]);
549 if (pv->value[opp]) {
550 /* Handle non-empty members only */
551 pv->value[opp] = optimize_vcore_voltage(pv, opp);
552 px = (struct volts *)vcores;
556 * Scan already handled non-empty members to see
557 * if we have a group and find the max voltage,
558 * which is set to the first occurance of the
559 * particular SMPS; the other group voltages are
562 ol = get_voltrail_opp(j);
564 (pv->pmic->i2c_slave_addr ==
565 px->pmic->i2c_slave_addr) &&
566 (pv->addr == px->addr)) {
567 /* Same PMIC, same SMPS */
568 if (pv->value[opp] > px->value[ol])
569 px->value[ol] = pv->value[opp];
577 debug("%d\n", pv->value[opp]);
581 opp = get_voltrail_opp(VOLT_CORE);
582 debug("cor: %d\n", vcores->core.value[opp]);
583 do_scale_vcore(vcores->core.addr, vcores->core.value[opp],
586 * IO delay recalibration should be done immediately after
587 * adjusting AVS voltages for VDD_CORE_L.
588 * Respective boards should call __recalibrate_iodelay()
589 * with proper mux, virtual and manual mode configurations.
591 #ifdef CONFIG_IODELAY_RECALIBRATION
592 recalibrate_iodelay();
595 opp = get_voltrail_opp(VOLT_MPU);
596 debug("mpu: %d\n", vcores->mpu.value[opp]);
597 do_scale_vcore(vcores->mpu.addr, vcores->mpu.value[opp],
599 /* Configure MPU ABB LDO after scale */
600 abb_setup(vcores->mpu.efuse.reg[opp],
601 (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
602 (*prcm)->prm_abbldo_mpu_setup,
603 (*prcm)->prm_abbldo_mpu_ctrl,
604 (*prcm)->prm_irqstatus_mpu_2,
605 vcores->mpu.abb_tx_done_mask,
608 opp = get_voltrail_opp(VOLT_MM);
609 debug("mm: %d\n", vcores->mm.value[opp]);
610 do_scale_vcore(vcores->mm.addr, vcores->mm.value[opp],
612 /* Configure MM ABB LDO after scale */
613 abb_setup(vcores->mm.efuse.reg[opp],
614 (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
615 (*prcm)->prm_abbldo_mm_setup,
616 (*prcm)->prm_abbldo_mm_ctrl,
617 (*prcm)->prm_irqstatus_mpu,
618 vcores->mm.abb_tx_done_mask,
621 opp = get_voltrail_opp(VOLT_GPU);
622 debug("gpu: %d\n", vcores->gpu.value[opp]);
623 do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp],
625 /* Configure GPU ABB LDO after scale */
626 abb_setup(vcores->gpu.efuse.reg[opp],
627 (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
628 (*prcm)->prm_abbldo_gpu_setup,
629 (*prcm)->prm_abbldo_gpu_ctrl,
630 (*prcm)->prm_irqstatus_mpu,
631 vcores->gpu.abb_tx_done_mask,
634 opp = get_voltrail_opp(VOLT_EVE);
635 debug("eve: %d\n", vcores->eve.value[opp]);
636 do_scale_vcore(vcores->eve.addr, vcores->eve.value[opp],
638 /* Configure EVE ABB LDO after scale */
639 abb_setup(vcores->eve.efuse.reg[opp],
640 (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
641 (*prcm)->prm_abbldo_eve_setup,
642 (*prcm)->prm_abbldo_eve_ctrl,
643 (*prcm)->prm_irqstatus_mpu,
644 vcores->eve.abb_tx_done_mask,
647 opp = get_voltrail_opp(VOLT_IVA);
648 debug("iva: %d\n", vcores->iva.value[opp]);
649 do_scale_vcore(vcores->iva.addr, vcores->iva.value[opp],
651 /* Configure IVA ABB LDO after scale */
652 abb_setup(vcores->iva.efuse.reg[opp],
653 (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
654 (*prcm)->prm_abbldo_iva_setup,
655 (*prcm)->prm_abbldo_iva_ctrl,
656 (*prcm)->prm_irqstatus_mpu,
657 vcores->iva.abb_tx_done_mask,
661 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
663 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
664 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
665 debug("Enable clock domain - %x\n", clkctrl_reg);
668 static inline void disable_clock_domain(u32 const clkctrl_reg)
670 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
671 CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
672 CD_CLKCTRL_CLKTRCTRL_SHIFT);
673 debug("Disable clock domain - %x\n", clkctrl_reg);
676 static inline void wait_for_clk_enable(u32 clkctrl_addr)
678 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
681 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
682 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
684 clkctrl = readl(clkctrl_addr);
685 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
686 MODULE_CLKCTRL_IDLEST_SHIFT;
688 printf("Clock enable failed for 0x%x idlest 0x%x\n",
689 clkctrl_addr, clkctrl);
695 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
698 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
699 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
700 debug("Enable clock module - %x\n", clkctrl_addr);
702 wait_for_clk_enable(clkctrl_addr);
705 static inline void wait_for_clk_disable(u32 clkctrl_addr)
707 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
710 while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
711 clkctrl = readl(clkctrl_addr);
712 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
713 MODULE_CLKCTRL_IDLEST_SHIFT;
715 printf("Clock disable failed for 0x%x idlest 0x%x\n",
716 clkctrl_addr, clkctrl);
722 static inline void disable_clock_module(u32 const clkctrl_addr,
723 u32 wait_for_disable)
725 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
726 MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
727 MODULE_CLKCTRL_MODULEMODE_SHIFT);
728 debug("Disable clock module - %x\n", clkctrl_addr);
729 if (wait_for_disable)
730 wait_for_clk_disable(clkctrl_addr);
733 void freq_update_core(void)
735 u32 freq_config1 = 0;
736 const struct dpll_params *core_dpll_params;
737 u32 omap_rev = omap_revision();
739 core_dpll_params = get_core_dpll_params(*dplls_data);
740 /* Put EMIF clock domain in sw wakeup mode */
741 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
742 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
743 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
744 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
746 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
747 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
749 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
750 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
752 freq_config1 |= (core_dpll_params->m2 <<
753 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
754 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
756 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
757 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
758 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
759 puts("FREQ UPDATE procedure failed!!");
764 * Putting EMIF in HW_AUTO is seen to be causing issues with
765 * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
766 * in OMAP5430 ES1.0 silicon
768 if (omap_rev != OMAP5430_ES1_0) {
769 /* Put EMIF clock domain back in hw auto mode */
770 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
771 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
772 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
773 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
777 void bypass_dpll(u32 const base)
779 do_bypass_dpll(base);
780 wait_for_bypass(base);
783 void lock_dpll(u32 const base)
789 static void setup_clocks_for_console(void)
791 /* Do not add any spl_debug prints in this function */
792 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
793 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
794 CD_CLKCTRL_CLKTRCTRL_SHIFT);
796 /* Enable all UARTs - console will be on one of them */
797 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
798 MODULE_CLKCTRL_MODULEMODE_MASK,
799 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
800 MODULE_CLKCTRL_MODULEMODE_SHIFT);
802 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
803 MODULE_CLKCTRL_MODULEMODE_MASK,
804 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
805 MODULE_CLKCTRL_MODULEMODE_SHIFT);
807 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
808 MODULE_CLKCTRL_MODULEMODE_MASK,
809 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
810 MODULE_CLKCTRL_MODULEMODE_SHIFT);
812 clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
813 MODULE_CLKCTRL_MODULEMODE_MASK,
814 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
815 MODULE_CLKCTRL_MODULEMODE_SHIFT);
817 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
818 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
819 CD_CLKCTRL_CLKTRCTRL_SHIFT);
822 void do_enable_clocks(u32 const *clk_domains,
823 u32 const *clk_modules_hw_auto,
824 u32 const *clk_modules_explicit_en,
829 /* Put the clock domains in SW_WKUP mode */
830 for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
831 enable_clock_domain(clk_domains[i],
832 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
835 /* Clock modules that need to be put in HW_AUTO */
836 for (i = 0; (i < max) && clk_modules_hw_auto &&
837 clk_modules_hw_auto[i]; i++) {
838 enable_clock_module(clk_modules_hw_auto[i],
839 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
843 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
844 for (i = 0; (i < max) && clk_modules_explicit_en &&
845 clk_modules_explicit_en[i]; i++) {
846 enable_clock_module(clk_modules_explicit_en[i],
847 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
851 /* Put the clock domains in HW_AUTO mode now */
852 for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
853 enable_clock_domain(clk_domains[i],
854 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
858 void do_disable_clocks(u32 const *clk_domains,
859 u32 const *clk_modules_disable,
865 /* Clock modules that need to be put in SW_DISABLE */
866 for (i = 0; (i < max) && clk_modules_disable[i]; i++)
867 disable_clock_module(clk_modules_disable[i],
870 /* Put the clock domains in SW_SLEEP mode */
871 for (i = 0; (i < max) && clk_domains[i]; i++)
872 disable_clock_domain(clk_domains[i]);
876 * setup_early_clocks() - Setup early clocks needed for SoC
878 * Setup clocks for console, SPL basic initialization clocks and initialize
879 * the timer. This is invoked prior prcm_init.
881 void setup_early_clocks(void)
883 switch (omap_hw_init_context()) {
884 case OMAP_INIT_CONTEXT_SPL:
885 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
886 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
887 setup_clocks_for_console();
888 enable_basic_clocks();
896 switch (omap_hw_init_context()) {
897 case OMAP_INIT_CONTEXT_SPL:
898 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
899 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
900 scale_vcores(*omap_vcores);
902 setup_warmreset_time();
908 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
909 enable_basic_uboot_clocks();
912 #if !defined(CONFIG_DM_I2C)
913 void gpi2c_init(void)
915 static int gpi2c = 1;
918 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
919 CONFIG_SYS_OMAP24_I2C_SLAVE);