1 // SPDX-License-Identifier: GPL-2.0+
5 * System information functions
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/clock.h>
19 #include <power/tps65910.h>
20 #include <linux/compiler.h>
22 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
25 * get_cpu_rev(void) - extract rev info
32 id = readl(DEVICE_ID);
33 rev = (id >> 28) & 0xff;
39 * get_cpu_type(void) - extract cpu info
41 u32 get_cpu_type(void)
46 id = readl(DEVICE_ID);
47 partnum = (id >> 12) & 0xffff;
53 * get_sysboot_value(void) - return SYS_BOOT[4:0]
55 u32 get_sysboot_value(void)
57 return readl(&cstat->statusreg) & SYSBOOT_MASK;
60 u32 get_sys_clk_index(void)
62 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
63 u32 ind = readl(&ctrl->statusreg);
67 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
68 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
69 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
70 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
71 else /* Value read from SYS BOOT pins */
73 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
74 CTRL_SYSBOOT_15_14_SHIFT);
78 #ifdef CONFIG_DISPLAY_CPUINFO
79 static char *cpu_revs[] = {
84 static char *cpu_revs_am43xx[] = {
89 static char *dev_types[] = {
96 * Print CPU information
98 int print_cpuinfo(void)
100 char *cpu_s, *sec_s, *rev_s;
101 char **cpu_rev_arr = cpu_revs;
103 switch (get_cpu_type()) {
112 cpu_rev_arr = cpu_revs_am43xx;
115 cpu_s = "Unknown CPU type";
119 if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
120 rev_s = cpu_rev_arr[get_cpu_rev()];
124 if (get_device_type() < ARRAY_SIZE(dev_types))
125 sec_s = dev_types[get_device_type()];
129 printf("CPU : %s-%s rev %s\n", cpu_s, sec_s, rev_s);
133 #endif /* CONFIG_DISPLAY_CPUINFO */
136 int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
140 sil_rev = readl(&cdev->deviceid) >> 28;
143 /* No efuse in PG 1.0. Use max speed */
145 } else if (sil_rev >= 1) {
146 /* Check what the efuse says our max speed is. */
147 int efuse_arm_mpu_max_freq, package_type;
148 efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
149 package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
152 /* PG 2.0, efuse may not be set. */
153 if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
154 PACKAGE_TYPE_RESERVED)
157 switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
158 case AM335X_ZCZ_1000:
159 return MPUPLL_M_1000;
173 /* unknown, use the PG1.0 max */
177 int am335x_get_mpu_vdd(int sil_rev, int frequency)
179 int sel_mask = am335x_get_tps65910_mpu_vdd(sil_rev, frequency);
182 case TPS65910_OP_REG_SEL_1_3_2_5:
184 case TPS65910_OP_REG_SEL_1_2_0:
186 case TPS65910_OP_REG_SEL_1_1_0:
193 int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
195 /* For PG2.0 and later, we have one set of values. */
199 return TPS65910_OP_REG_SEL_1_3_2_5;
201 return TPS65910_OP_REG_SEL_1_2_6;
203 return TPS65910_OP_REG_SEL_1_2_0;
207 return TPS65910_OP_REG_SEL_1_1_0;
211 /* Default to PG1.0 values. */
212 return TPS65910_OP_REG_SEL_1_2_6;