arch/arm/mach-omap2/am33xx/emif4.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * emif4.c
   4  *
   5  * AM33XX emif4 configuration file
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/ddr_defs.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <asm/emif.h>
  18
  19 static struct vtp_reg *vtpreg[2] = {
  20                                 (struct vtp_reg *)VTP0_CTRL_ADDR,
  21                                 (struct vtp_reg *)VTP1_CTRL_ADDR};
  22 #ifdef CONFIG_AM33XX
  23 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  24 #endif
  25 #ifdef CONFIG_AM43XX
  26 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  27 static struct cm_device_inst *cm_device =
  28                                 (struct cm_device_inst *)CM_DEVICE_INST;
  29 #endif
  30
  31 #ifdef CONFIG_TI814X
  32 void config_dmm(const struct dmm_lisa_map_regs *regs)
  33 {
  34         struct dmm_lisa_map_regs *hw_lisa_map_regs =
  35                                 (struct dmm_lisa_map_regs *)DMM_BASE;
  36
  37         enable_dmm_clocks();
  38
  39         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
  40         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
  41         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
  42         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
  43
  44         writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
  45         writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
  46         writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
  47         writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
  48 }
  49 #endif
  50
  51 static void config_vtp(int nr)
  52 {
  53         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
  54                         &vtpreg[nr]->vtp0ctrlreg);
  55         writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
  56                         &vtpreg[nr]->vtp0ctrlreg);
  57         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
  58                         &vtpreg[nr]->vtp0ctrlreg);
  59
  60         /* Poll for READY */
  61         while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
  62                         VTP_CTRL_READY)
  63                 ;
  64 }
  65
  66 void __weak ddr_pll_config(unsigned int ddrpll_m)
  67 {
  68 }
  69
  70 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
  71                 const struct ddr_data *data, const struct cmd_control *ctrl,
  72                 const struct emif_regs *regs, int nr)
  73 {
  74         ddr_pll_config(pll);
  75         config_vtp(nr);
  76         config_cmd_ctrl(ctrl, nr);
  77
  78         config_ddr_data(data, nr);
  79 #ifdef CONFIG_AM33XX
  80         config_io_ctrl(ioregs);
  81
  82         /* Set CKE to be controlled by EMIF/DDR PHY */
  83         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
  84
  85 #endif
  86 #ifdef CONFIG_AM43XX
  87         writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
  88         while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
  89                 ;
  90
  91         config_io_ctrl(ioregs);
  92
  93         /* Set CKE to be controlled by EMIF/DDR PHY */
  94         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
  95
  96         if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
  97 #ifndef CONFIG_SPL_RTC_DDR_SUPPORT
  98                 /* Allow EMIF to control DDR_RESET */
  99                 writel(0x00000000, &ddrctrl->ddrioctrl);
 100 #else
 101                 /* Override EMIF DDR_RESET control */
 102                 writel(0x80000000, &ddrctrl->ddrioctrl);
 103 #endif /* CONFIG_SPL_RTC_DDR_SUPPORT */
 104 #endif
 105
 106         /* Program EMIF instance */
 107         config_ddr_phy(regs, nr);
 108         set_sdram_timings(regs, nr);
 109         if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
 110                 config_sdram_emif4d5(regs, nr);
 111         else
 112                 config_sdram(regs, nr);
 113 }