arch/arm/mach-omap2/am33xx/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * DDR Configuration for AM33xx devices.
   4  *
   5  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <asm/arch/cpu.h>
   9 #include <asm/arch/ddr_defs.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/io.h>
  12 #include <asm/emif.h>
  13
  14 /**
  15  * Base address for EMIF instances
  16  */
  17 static struct emif_reg_struct *emif_reg[2] = {
  18                                 (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  19                                 (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
  20
  21 /**
  22  * Base addresses for DDR PHY cmd/data regs
  23  */
  24 static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  25                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  26                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
  27
  28 static struct ddr_data_regs *ddr_data_reg[2] = {
  29                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  30                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
  31
  32 /**
  33  * Base address for ddr io control instances
  34  */
  35 static struct ddr_cmdtctrl *ioctrl_reg = {
  36                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  37
  38 static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
  39 {
  40         u32 mr;
  41
  42         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  43         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  44
  45         mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
  46         debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
  47         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  48             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  49             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  50                 return mr & 0xff;
  51         else
  52                 return mr;
  53 }
  54
  55 static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
  56 {
  57         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  58         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  59         writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
  60 }
  61
  62 static void configure_mr(int nr, u32 cs)
  63 {
  64         u32 mr_addr;
  65
  66         while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  67                 ;
  68         set_mr(nr, cs, LPDDR2_MR10, 0x56);
  69
  70         set_mr(nr, cs, LPDDR2_MR1, 0x43);
  71         set_mr(nr, cs, LPDDR2_MR2, 0x2);
  72
  73         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  74         set_mr(nr, cs, mr_addr, 0x2);
  75 }
  76
  77 /*
  78  * Configure EMIF4D5 registers and MR registers For details about these magic
  79  * values please see the EMIF registers section of the TRM.
  80  */
  81 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  82 {
  83 #ifdef CONFIG_AM43XX
  84         struct prm_device_inst *prm_device =
  85                         (struct prm_device_inst *)PRM_DEVICE_INST;
  86 #endif
  87
  88         writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  89         writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  90         writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  91
  92         writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
  93         writel(regs->emif_rd_wr_lvl_rmp_win,
  94                &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
  95         writel(regs->emif_rd_wr_lvl_rmp_ctl,
  96                &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  97         writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
  98         writel(regs->emif_rd_wr_exec_thresh,
  99                &emif_reg[nr]->emif_rd_wr_exec_thresh);
 100
 101         /*
 102          * for most SOCs these registers won't need to be changed so only
 103          * write to these registers if someone explicitly has set the
 104          * register's value.
 105          */
 106         if(regs->emif_cos_config) {
 107                 writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
 108                 writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
 109                 writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
 110                 writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
 111         }
 112
 113         /*
 114          * Sequence to ensure that the PHY is in a known state prior to
 115          * startting hardware leveling.  Also acts as to latch some state from
 116          * the EMIF into the PHY.
 117          */
 118         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 119         writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 120         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 121
 122         clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 123                         EMIF_REG_INITREF_DIS_MASK);
 124
 125         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 126         writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 127
 128         /* Wait 1ms because of L3 timeout error */
 129         udelay(1000);
 130
 131         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 132         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 133
 134 #ifdef CONFIG_AM43XX
 135         /*
 136          * Disable EMIF_DEVOFF
 137          * -> Cold Boot: This is just rewriting the default register value.
 138          * -> RTC Resume: Must disable DEVOFF before leveling.
 139          */
 140         writel(0, &prm_device->emif_ctrl);
 141 #endif
 142
 143         /* Perform hardware leveling for DDR3 */
 144         if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
 145                 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
 146                        0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 147                 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
 148                        0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 149
 150                 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
 151
 152                 /* Enable read leveling */
 153                 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 154
 155                 /* Wait 1ms because of L3 timeout error */
 156                 udelay(1000);
 157
 158                 /*
 159                  * Enable full read and write leveling.  Wait for read and write
 160                  * leveling bit to clear RDWRLVLFULL_START bit 31
 161                  */
 162                 while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
 163                       != 0)
 164                         ;
 165
 166                 /* Check the timeout register to see if leveling is complete */
 167                 if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
 168                         puts("DDR3 H/W leveling incomplete with errors\n");
 169
 170         } else {
 171                 /* DDR2 */
 172                 configure_mr(nr, 0);
 173                 configure_mr(nr, 1);
 174         }
 175 }
 176
 177 /**
 178  * Configure SDRAM
 179  */
 180 void config_sdram(const struct emif_regs *regs, int nr)
 181 {
 182 #ifdef CONFIG_TI816X
 183         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 184         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
 185         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 186         writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* initially a large refresh period */
 187         writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* trigger initialization           */
 188         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 189 #else
 190         if (regs->zq_config) {
 191                 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 192                 writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 193                 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 194
 195                 /* Trigger initialization */
 196                 writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
 197                 /* Wait 1ms because of L3 timeout error */
 198                 udelay(1000);
 199
 200                 /* Write proper sdram_ref_cref_ctrl value */
 201                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 202                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 203         }
 204         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 205         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 206         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 207
 208         /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
 209         if (regs->ocp_config)
 210                 writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
 211 #endif
 212 }
 213
 214 /**
 215  * Set SDRAM timings
 216  */
 217 void set_sdram_timings(const struct emif_regs *regs, int nr)
 218 {
 219         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
 220         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
 221         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
 222         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
 223         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
 224         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 225 }
 226
 227 /*
 228  * Configure EXT PHY registers for software leveling
 229  */
 230 static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
 231 {
 232         u32 *ext_phy_ctrl_base = 0;
 233         u32 *emif_ext_phy_ctrl_base = 0;
 234         __maybe_unused const u32 *ext_phy_ctrl_const_regs;
 235         u32 i = 0;
 236         __maybe_unused u32 size;
 237
 238         ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
 239         emif_ext_phy_ctrl_base =
 240                         (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 241
 242         /* Configure external phy control timing registers */
 243         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 244                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 245                 /* Update shadow registers */
 246                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 247         }
 248
 249 #ifdef CONFIG_AM43XX
 250         /*
 251          * External phy 6-24 registers do not change with ddr frequency.
 252          * These only need to be set on DDR2 on AM43xx.
 253          */
 254         emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
 255
 256         if (!size)
 257                 return;
 258
 259         for (i = 0; i < size; i++) {
 260                 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
 261                 /* Update shadow registers */
 262                 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
 263         }
 264 #endif
 265 }
 266
 267 /*
 268  * Configure EXT PHY registers for hardware leveling
 269  */
 270 static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
 271 {
 272         /*
 273          * Enable hardware leveling on the EMIF.  For details about these
 274          * magic values please see the EMIF registers section of the TRM.
 275          */
 276         if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
 277                 /* PHY_INVERT_CLKOUT = 1 */
 278                 writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 279                 writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
 280         } else {
 281                 /* PHY_INVERT_CLKOUT = 0 */
 282                 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 283                 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
 284         }
 285
 286         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
 287         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
 288         writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
 289         writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
 290         writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
 291         writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
 292         writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
 293         writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
 294         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
 295         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
 296         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
 297         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
 298         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
 299         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
 300         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
 301         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
 302         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
 303         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
 304         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
 305         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
 306         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
 307         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
 308         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
 309         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
 310         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
 311         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
 312         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
 313         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
 314         writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 315         writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 316
 317         /*
 318          * Sequence to ensure that the PHY is again in a known state after
 319          * hardware leveling.
 320          */
 321         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 322         writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 323         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 324 }
 325
 326 /**
 327  * Configure DDR PHY
 328  */
 329 void config_ddr_phy(const struct emif_regs *regs, int nr)
 330 {
 331         /*
 332          * Disable initialization and refreshes for now until we finish
 333          * programming EMIF regs and set time between rising edge of
 334          * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
 335          * We currently hardcode a value based on a max expected frequency
 336          * of 400MHz.
 337          */
 338         writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
 339                 &emif_reg[nr]->emif_sdram_ref_ctrl);
 340
 341         writel(regs->emif_ddr_phy_ctlr_1,
 342                 &emif_reg[nr]->emif_ddr_phy_ctrl_1);
 343         writel(regs->emif_ddr_phy_ctlr_1,
 344                 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 345
 346         if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
 347                 if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
 348                         ext_phy_settings_hwlvl(regs, nr);
 349                 else
 350                         ext_phy_settings_swlvl(regs, nr);
 351         }
 352 }
 353
 354 /**
 355  * Configure DDR CMD control registers
 356  */
 357 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 358 {
 359         if (!cmd)
 360                 return;
 361
 362         writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
 363         writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 364
 365         writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
 366         writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 367
 368         writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
 369         writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 370 }
 371
 372 /**
 373  * Configure DDR DATA registers
 374  */
 375 void config_ddr_data(const struct ddr_data *data, int nr)
 376 {
 377         int i;
 378
 379         if (!data)
 380                 return;
 381
 382         for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 383                 writel(data->datardsratio0,
 384                         &(ddr_data_reg[nr]+i)->dt0rdsratio0);
 385                 writel(data->datawdsratio0,
 386                         &(ddr_data_reg[nr]+i)->dt0wdsratio0);
 387                 writel(data->datawiratio0,
 388                         &(ddr_data_reg[nr]+i)->dt0wiratio0);
 389                 writel(data->datagiratio0,
 390                         &(ddr_data_reg[nr]+i)->dt0giratio0);
 391                 writel(data->datafwsratio0,
 392                         &(ddr_data_reg[nr]+i)->dt0fwsratio0);
 393                 writel(data->datawrsratio0,
 394                         &(ddr_data_reg[nr]+i)->dt0wrsratio0);
 395         }
 396 }
 397
 398 void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 399 {
 400         if (!ioregs)
 401                 return;
 402
 403         writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
 404         writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
 405         writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
 406         writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
 407         writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
 408 #ifdef CONFIG_AM43XX
 409         writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
 410         writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
 411         writel(ioregs->emif_sdram_config_ext,
 412                &ioctrl_reg->emif_sdram_config_ext);
 413 #endif
 414 }