1 // SPDX-License-Identifier: GPL-2.0+
5 * Clocks for TI814X based boards
7 * Copyright (C) 2013, Texas Instruments, Incorporated
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/hardware.h>
17 #define PRCM_MOD_EN 0x2
23 #define L3_OSC_SRC OSC_SRC0
27 #define DCO_HS2_MIN 500
28 #define DCO_HS2_MAX 1000
29 #define DCO_HS1_MIN 1000
30 #define DCO_HS1_MAX 2000
32 #define SELFREQDCO_HS2 0x00000801
33 #define SELFREQDCO_HS1 0x00001001
38 #define MPU_CLKCTRL 0x1
43 #define L3_CLKCTRL 0x801
48 #define DDR_CLKCTRL 0x801
50 /* ADPLLJ register values */
51 #define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
52 #define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
53 #define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
54 #define ADPLLJ_CLKCTRL_IDLE (1 << 23)
55 #define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
56 #define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
57 #define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
58 #define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
59 #define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
60 #define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
61 #define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
62 #define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
63 ADPLLJ_CLKCTRL_CLKOUTEN | \
64 ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
65 ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
67 #define ADPLLJ_STATUS_PHASELOCK (1 << 10)
68 #define ADPLLJ_STATUS_FREQLOCK (1 << 9)
69 #define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
70 ADPLLJ_STATUS_FREQLOCK)
71 #define ADPLLJ_STATUS_BYPASSACK (1 << 8)
72 #define ADPLLJ_STATUS_BYPASS (1 << 0)
73 #define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
76 #define ADPLLJ_TENABLE_ENB (1 << 0)
77 #define ADPLLJ_TENABLEDIV_ENB (1 << 0)
79 #define ADPLLJ_M2NDIV_M2SHIFT 16
81 #define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
82 #define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
83 #define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
89 unsigned int tenablediv;
94 unsigned int fracctrl;
97 unsigned int rampctrl;
100 #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
102 #define ENET_CLKCTRL_CMPL 0x30000
104 #define SATA_PLL_BASE (CTRL_BASE + 0x0720)
107 unsigned int pllcfg0;
108 unsigned int pllcfg1;
109 unsigned int pllcfg2;
110 unsigned int pllcfg3;
111 unsigned int pllcfg4;
112 unsigned int pllstatus;
113 unsigned int rxstatus;
114 unsigned int txstatus;
115 unsigned int testcfg;
118 #define SEL_IN_FREQ (0x1 << 31)
119 #define DIGCLRZ (0x1 << 30)
120 #define ENDIGLDO (0x1 << 4)
121 #define APLL_CP_CURR (0x1 << 3)
122 #define ENBGSC_REF (0x1 << 2)
123 #define ENPLLLDO (0x1 << 1)
124 #define ENPLL (0x1 << 0)
126 #define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
127 #define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
128 #define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
129 #define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
132 #define PLL_LOCK (0x1 << 0)
134 #define ENSATAMODE (0x1 << 31)
135 #define PLLREFSEL (0x1 << 30)
136 #define MDIVINT (0x4b << 18)
137 #define EN_CLKAUX (0x1 << 5)
138 #define EN_CLK125M (0x1 << 4)
139 #define EN_CLK100M (0x1 << 3)
140 #define EN_CLK50M (0x1 << 2)
142 #define SATA_PLLCFG1 (ENSATAMODE | \
150 #define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
151 #define PLLDO_EN_LDO_STABLE (0x1 << 11)
152 #define PLLDO_EN_BUF_CUR (0x1 << 7)
153 #define PLLDO_EN_LP (0x1 << 6)
154 #define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
156 #define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
157 PLLDO_EN_LDO_STABLE | \
160 PLLDO_CTRL_TRIM_1_4V)
162 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
163 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
164 const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
167 * Enable the peripheral clock for required peripherals
169 static void enable_per_clocks(void)
172 writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
173 while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
177 writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
178 writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
179 while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
181 writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
182 while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
186 writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
187 writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
188 while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
193 * select the HS1 or HS2 for DCO Freq
196 static u32 pll_dco_freq_sel(u32 clkout_dco)
198 if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
199 return SELFREQDCO_HS2;
200 else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
201 return SELFREQDCO_HS1;
207 * select the sigma delta config
208 * return: sigma delta val
210 static u32 pll_sigma_delta_val(u32 clkout_dco)
214 sig_val = (clkout_dco + 225) / 250;
215 sig_val = sig_val << 24;
221 * configure individual ADPLLJ
223 static void pll_config(u32 base, u32 n, u32 m, u32 m2,
224 u32 clkctrl_val, int adpllj)
226 const struct ad_pll *adpll = (struct ad_pll *)base;
227 u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
228 u32 sig_val = 0, hs_mod = 0;
230 m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
233 /* calculate clkout_dco */
234 clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
236 /* sigma delta & Hs mode selection skip for ADPLLS*/
238 sig_val = pll_sigma_delta_val(clkout_dco);
239 hs_mod = pll_dco_freq_sel(clkout_dco);
243 read_clkctrl = readl(&adpll->clkctrl);
244 writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
245 while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
246 != ADPLLJ_STATUS_BYPASSANDACK)
250 read_clkctrl = readl(&adpll->clkctrl);
251 writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
254 * ref_clk = 20/(n + 1);
255 * clkout_dco = ref_clk * m;
256 * clk_out = clkout_dco/m2;
258 read_clkctrl = readl(&adpll->clkctrl) &
259 ~(ADPLLJ_CLKCTRL_LPMODE |
260 ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
261 ADPLLJ_CLKCTRL_REGM4XEN);
262 writel(m2nval, &adpll->m2ndiv);
263 writel(mn2val, &adpll->mn2div);
265 /* Skip for modena(ADPLLS) */
267 writel(sig_val, &adpll->fracdiv);
268 writel((read_clkctrl | hs_mod), &adpll->clkctrl);
271 /* Load M2, N2 dividers of ADPLL */
272 writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
273 writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
275 /* Load M, N dividers of ADPLL */
276 writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
277 writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
279 /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
280 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
282 writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
285 /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
286 read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
287 writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
289 /* Wait for phase and freq lock */
290 while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
291 ADPLLJ_STATUS_PHSFRQLOCK)
295 static void unlock_pll_control_mmr(void)
297 /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
298 writel(0x1EDA4C3D, 0x481C5040);
299 writel(0x2FF1AC2B, 0x48140060);
300 writel(0xF757FDC0, 0x48140064);
301 writel(0xE2BC3A6D, 0x48140068);
302 writel(0x1EBF131D, 0x4814006c);
303 writel(0x6F361E05, 0x48140070);
306 static void mpu_pll_config(void)
308 pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
311 static void l3_pll_config(void)
313 u32 l3_osc_src, rd_osc_src = 0;
315 l3_osc_src = L3_OSC_SRC;
316 rd_osc_src = readl(OSC_SRC_CTRL);
318 if (OSC_SRC0 == l3_osc_src)
319 writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
321 writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
323 pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
326 void ddr_pll_config(unsigned int ddrpll_m)
328 pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
331 void sata_pll_config(void)
334 * This sequence for configuring the SATA PLL
335 * resident in the control module is documented
336 * in TI8148 TRM section 21.3.1
338 writel(SATA_PLLCFG1, &spll->pllcfg1);
341 writel(SATA_PLLCFG3, &spll->pllcfg3);
344 writel(SATA_PLLCFG0_1, &spll->pllcfg0);
347 writel(SATA_PLLCFG0_2, &spll->pllcfg0);
350 writel(SATA_PLLCFG0_3, &spll->pllcfg0);
353 writel(SATA_PLLCFG0_4, &spll->pllcfg0);
356 while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
360 void enable_dmm_clocks(void)
362 writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
363 writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
364 writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
365 while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
367 writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
368 while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
370 while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
372 writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
373 while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
375 writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
376 while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
380 void setup_clocks_for_console(void)
382 unlock_pll_control_mmr();
384 writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
385 while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
389 void setup_early_clocks(void)
391 setup_clocks_for_console();
395 * Configure the PLL/PRCM for necessary peripherals
399 /* Enable the control module */
400 writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
407 /* Enable the required peripherals */