1 // SPDX-License-Identifier: GPL-2.0+
5 * Clock synthesizer apis
7 * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
12 #include <asm/arch/clk_synthesizer.h>
16 * clk_synthesizer_reg_read - Read register from synthesizer.
17 * @addr: addr within the i2c device
18 * buf: Buffer to which value is to be read.
20 * For reading the register from this clock synthesizer, a command needs to
21 * be send along with enabling byte read more, and then read can happen.
22 * Returns 0 on success
24 static int clk_synthesizer_reg_read(int addr, uint8_t *buf)
29 addr = addr | CLK_SYNTHESIZER_BYTE_MODE;
31 /* Send the command byte */
32 rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
34 printf("Failed to send command to clock synthesizer\n");
37 return i2c_read(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
41 * clk_synthesizer_reg_write - Write a value to register in synthesizer.
42 * @addr: addr within the i2c device
43 * val: Value to be written in the addr.
45 * Enable the byte read mode in the address and start the i2c transfer.
46 * Returns 0 on success
48 static int clk_synthesizer_reg_write(int addr, uint8_t val)
53 /* Enable byte write */
54 cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE;
57 rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2);
59 printf("Clock synthesizer reg write failed at addr = 0x%x\n",
65 * setup_clock_syntherizer - Program the clock synthesizer to get the desired
67 * @data: Data containing the desired output
69 * This is a PLL-based high performance synthesizer which gives 3 outputs
70 * as per the PLL_DIV and load capacitor programmed.
72 int setup_clock_synthesizer(struct clk_synth *data)
77 rc = i2c_probe(CLK_SYNTHESIZER_I2C_ADDR);
79 printf("i2c probe failed at address 0x%x\n",
80 CLK_SYNTHESIZER_I2C_ADDR);
84 rc = clk_synthesizer_reg_read(CLK_SYNTHESIZER_ID_REG, &val);
88 /* Crystal Load capacitor selection */
89 rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_XCSEL, data->capacitor);
92 rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_MUX_REG, data->mux);
95 rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2);
98 rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3);