4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <debug_uart.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/omap.h>
20 #include <asm/arch/ddr_defs.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/mem.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/sys_proto.h>
32 #include <linux/errno.h>
33 #include <linux/compiler.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/musb.h>
37 #include <asm/omap_musb.h>
38 #include <asm/davinci_rtc.h>
40 DECLARE_GLOBAL_DATA_PTR;
44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
48 /* dram_init must store complete ramsize in gd->ram_size */
49 gd->ram_size = get_ram_size(
50 (void *)CONFIG_SYS_SDRAM_BASE,
51 CONFIG_MAX_RAM_BANK_SIZE);
55 int dram_init_banksize(void)
57 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
58 gd->bd->bi_dram[0].size = gd->ram_size;
63 #if !CONFIG_IS_ENABLED(OF_CONTROL)
64 static const struct ns16550_platdata am33xx_serial[] = {
65 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
66 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
67 # ifdef CONFIG_SYS_NS16550_COM2
68 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
69 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
70 # ifdef CONFIG_SYS_NS16550_COM3
71 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
72 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
73 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
74 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
75 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
76 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
77 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
78 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
83 U_BOOT_DEVICES(am33xx_uarts) = {
84 { "ns16550_serial", &am33xx_serial[0] },
85 # ifdef CONFIG_SYS_NS16550_COM2
86 { "ns16550_serial", &am33xx_serial[1] },
87 # ifdef CONFIG_SYS_NS16550_COM3
88 { "ns16550_serial", &am33xx_serial[2] },
89 { "ns16550_serial", &am33xx_serial[3] },
90 { "ns16550_serial", &am33xx_serial[4] },
91 { "ns16550_serial", &am33xx_serial[5] },
97 static const struct omap_gpio_platdata am33xx_gpio[] = {
98 { 0, AM33XX_GPIO0_BASE },
99 { 1, AM33XX_GPIO1_BASE },
100 { 2, AM33XX_GPIO2_BASE },
101 { 3, AM33XX_GPIO3_BASE },
103 { 4, AM33XX_GPIO4_BASE },
104 { 5, AM33XX_GPIO5_BASE },
108 U_BOOT_DEVICES(am33xx_gpios) = {
109 { "gpio_omap", &am33xx_gpio[0] },
110 { "gpio_omap", &am33xx_gpio[1] },
111 { "gpio_omap", &am33xx_gpio[2] },
112 { "gpio_omap", &am33xx_gpio[3] },
114 { "gpio_omap", &am33xx_gpio[4] },
115 { "gpio_omap", &am33xx_gpio[5] },
121 #ifndef CONFIG_DM_GPIO
122 static const struct gpio_bank gpio_bank_am33xx[] = {
123 { (void *)AM33XX_GPIO0_BASE },
124 { (void *)AM33XX_GPIO1_BASE },
125 { (void *)AM33XX_GPIO2_BASE },
126 { (void *)AM33XX_GPIO3_BASE },
128 { (void *)AM33XX_GPIO4_BASE },
129 { (void *)AM33XX_GPIO5_BASE },
133 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
136 #if defined(CONFIG_MMC_OMAP_HS)
137 int cpu_mmc_init(bd_t *bis)
141 ret = omap_mmc_init(0, 0, 0, -1, -1);
145 return omap_mmc_init(1, 0, 0, -1, -1);
149 /* AM33XX has two MUSB controllers which can be host or gadget */
150 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
151 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
152 (!defined(CONFIG_DM_USB))
153 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
155 /* USB 2.0 PHY Control */
156 #define CM_PHY_PWRDN (1 << 0)
157 #define CM_PHY_OTG_PWRDN (1 << 1)
158 #define OTGVDET_EN (1 << 19)
159 #define OTGSESSENDEN (1 << 20)
161 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
164 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
165 OTGVDET_EN | OTGSESSENDEN);
167 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
171 static struct musb_hdrc_config musb_config = {
178 #ifdef CONFIG_AM335X_USB0
179 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
181 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
184 struct omap_musb_board_data otg0_board_data = {
185 .set_phy_power = am33xx_otg0_set_phy_power,
188 static struct musb_hdrc_platform_data otg0_plat = {
189 .mode = CONFIG_AM335X_USB0_MODE,
190 .config = &musb_config,
192 .platform_ops = &musb_dsps_ops,
193 .board_data = &otg0_board_data,
197 #ifdef CONFIG_AM335X_USB1
198 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
200 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
203 struct omap_musb_board_data otg1_board_data = {
204 .set_phy_power = am33xx_otg1_set_phy_power,
207 static struct musb_hdrc_platform_data otg1_plat = {
208 .mode = CONFIG_AM335X_USB1_MODE,
209 .config = &musb_config,
211 .platform_ops = &musb_dsps_ops,
212 .board_data = &otg1_board_data,
217 int arch_misc_init(void)
219 #ifndef CONFIG_DM_USB
220 #ifdef CONFIG_AM335X_USB0
221 musb_register(&otg0_plat, &otg0_board_data,
222 (void *)USB0_OTG_BASE);
224 #ifdef CONFIG_AM335X_USB1
225 musb_register(&otg1_plat, &otg1_board_data,
226 (void *)USB1_OTG_BASE);
232 ret = uclass_first_device(UCLASS_MISC, &dev);
236 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
237 ret = usb_ether_init();
239 error("USB ether init failed\n");
247 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
249 * In the case of non-SPL based booting we'll want to call these
250 * functions a tiny bit later as it will require gd to be set and cleared
251 * and that's not true in s_init in this case so we cannot do it there.
253 int board_early_init_f(void)
262 * This function is the place to do per-board things such as ramp up the
263 * MPU clock frequency.
265 __weak void am33xx_spl_board_init(void)
269 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
270 static void rtc32k_enable(void)
272 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
275 * Unlock the RTC's registers. For more details please see the
276 * RTC_SS section of the TRM. In order to unlock we need to
277 * write these specific values (keys) in this order.
279 writel(RTC_KICK0R_WE, &rtc->kick0r);
280 writel(RTC_KICK1R_WE, &rtc->kick1r);
282 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
283 writel((1 << 3) | (1 << 6), &rtc->osc);
287 static void uart_soft_reset(void)
289 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
292 regval = readl(&uart_base->uartsyscfg);
293 regval |= UART_RESET;
294 writel(regval, &uart_base->uartsyscfg);
295 while ((readl(&uart_base->uartsyssts) &
296 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
299 /* Disable smart idle */
300 regval = readl(&uart_base->uartsyscfg);
301 regval |= UART_SMART_IDLE_EN;
302 writel(regval, &uart_base->uartsyscfg);
305 static void watchdog_disable(void)
307 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
309 writel(0xAAAA, &wdtimer->wdtwspr);
310 while (readl(&wdtimer->wdtwwps) != 0x0)
312 writel(0x5555, &wdtimer->wdtwspr);
313 while (readl(&wdtimer->wdtwwps) != 0x0)
321 void early_system_init(void)
324 * The ROM will only have set up sufficient pinmux to allow for the
325 * first 4KiB NOR to be read, we must finish doing what we know of
326 * the NOR mux in this space in order to continue.
328 #ifdef CONFIG_NOR_BOOT
329 enable_norboot_pin_mux();
333 setup_early_clocks();
335 #ifdef CONFIG_DEBUG_UART_OMAP
338 #ifdef CONFIG_TI_I2C_BOARD_DETECT
341 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
342 /* Enable RTC32K clock */
347 #ifdef CONFIG_SPL_BUILD
348 void board_init_f(ulong dummy)
351 board_early_init_f();
353 /* dram_init must store complete ramsize in gd->ram_size */
354 gd->ram_size = get_ram_size(
355 (void *)CONFIG_SYS_SDRAM_BASE,
356 CONFIG_MAX_RAM_BANK_SIZE);
362 int arch_cpu_init_dm(void)
364 #ifndef CONFIG_SKIP_LOWLEVEL_INIT