1 // SPDX-License-Identifier: GPL-2.0+
5 * Common board functions for AM33XX based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
12 #include <debug_uart.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/i2c.h>
23 #include <asm/arch/mem.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/sys_proto.h>
29 #include <asm/omap_common.h>
33 #include <linux/errno.h>
34 #include <linux/compiler.h>
35 #include <linux/usb/ch9.h>
36 #include <linux/usb/gadget.h>
37 #include <linux/usb/musb.h>
38 #include <asm/omap_musb.h>
39 #include <asm/davinci_rtc.h>
41 DECLARE_GLOBAL_DATA_PTR;
45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
49 /* dram_init must store complete ramsize in gd->ram_size */
50 gd->ram_size = get_ram_size(
51 (void *)CONFIG_SYS_SDRAM_BASE,
52 CONFIG_MAX_RAM_BANK_SIZE);
56 int dram_init_banksize(void)
58 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
59 gd->bd->bi_dram[0].size = gd->ram_size;
64 #if !CONFIG_IS_ENABLED(OF_CONTROL)
65 static const struct ns16550_platdata am33xx_serial[] = {
66 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
67 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
68 # ifdef CONFIG_SYS_NS16550_COM2
69 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
70 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
71 # ifdef CONFIG_SYS_NS16550_COM3
72 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
73 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
74 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
75 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
76 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
77 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
78 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
79 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
84 U_BOOT_DEVICES(am33xx_uarts) = {
85 { "ns16550_serial", &am33xx_serial[0] },
86 # ifdef CONFIG_SYS_NS16550_COM2
87 { "ns16550_serial", &am33xx_serial[1] },
88 # ifdef CONFIG_SYS_NS16550_COM3
89 { "ns16550_serial", &am33xx_serial[2] },
90 { "ns16550_serial", &am33xx_serial[3] },
91 { "ns16550_serial", &am33xx_serial[4] },
92 { "ns16550_serial", &am33xx_serial[5] },
98 static const struct omap_i2c_platdata am33xx_i2c[] = {
99 { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
100 { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
101 { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
104 U_BOOT_DEVICES(am33xx_i2c) = {
105 { "i2c_omap", &am33xx_i2c[0] },
106 { "i2c_omap", &am33xx_i2c[1] },
107 { "i2c_omap", &am33xx_i2c[2] },
111 #ifdef CONFIG_DM_GPIO
112 static const struct omap_gpio_platdata am33xx_gpio[] = {
113 { 0, AM33XX_GPIO0_BASE },
114 { 1, AM33XX_GPIO1_BASE },
115 { 2, AM33XX_GPIO2_BASE },
116 { 3, AM33XX_GPIO3_BASE },
118 { 4, AM33XX_GPIO4_BASE },
119 { 5, AM33XX_GPIO5_BASE },
123 U_BOOT_DEVICES(am33xx_gpios) = {
124 { "gpio_omap", &am33xx_gpio[0] },
125 { "gpio_omap", &am33xx_gpio[1] },
126 { "gpio_omap", &am33xx_gpio[2] },
127 { "gpio_omap", &am33xx_gpio[3] },
129 { "gpio_omap", &am33xx_gpio[4] },
130 { "gpio_omap", &am33xx_gpio[5] },
136 #ifndef CONFIG_DM_GPIO
137 static const struct gpio_bank gpio_bank_am33xx[] = {
138 { (void *)AM33XX_GPIO0_BASE },
139 { (void *)AM33XX_GPIO1_BASE },
140 { (void *)AM33XX_GPIO2_BASE },
141 { (void *)AM33XX_GPIO3_BASE },
143 { (void *)AM33XX_GPIO4_BASE },
144 { (void *)AM33XX_GPIO5_BASE },
148 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
151 #if defined(CONFIG_MMC_OMAP_HS)
152 int cpu_mmc_init(bd_t *bis)
156 ret = omap_mmc_init(0, 0, 0, -1, -1);
160 return omap_mmc_init(1, 0, 0, -1, -1);
165 * RTC only with DDR in self-refresh mode magic value, checked against during
166 * boot to see if we have a valid config. This should be in sync with the value
167 * that will be in drivers/soc/ti/pm33xx.c.
169 #define RTC_MAGIC_VAL 0x8cd0
171 /* Board type field bit shift for RTC only with DDR in self-refresh mode */
172 #define RTC_BOARD_TYPE_SHIFT 16
174 /* AM33XX has two MUSB controllers which can be host or gadget */
175 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
176 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
177 (!defined(CONFIG_DM_USB))
178 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
180 /* USB 2.0 PHY Control */
181 #define CM_PHY_PWRDN (1 << 0)
182 #define CM_PHY_OTG_PWRDN (1 << 1)
183 #define OTGVDET_EN (1 << 19)
184 #define OTGSESSENDEN (1 << 20)
186 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
189 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
190 OTGVDET_EN | OTGSESSENDEN);
192 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
196 static struct musb_hdrc_config musb_config = {
203 #ifdef CONFIG_AM335X_USB0
204 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
206 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
209 struct omap_musb_board_data otg0_board_data = {
210 .set_phy_power = am33xx_otg0_set_phy_power,
213 static struct musb_hdrc_platform_data otg0_plat = {
214 .mode = CONFIG_AM335X_USB0_MODE,
215 .config = &musb_config,
217 .platform_ops = &musb_dsps_ops,
218 .board_data = &otg0_board_data,
222 #ifdef CONFIG_AM335X_USB1
223 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
225 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
228 struct omap_musb_board_data otg1_board_data = {
229 .set_phy_power = am33xx_otg1_set_phy_power,
232 static struct musb_hdrc_platform_data otg1_plat = {
233 .mode = CONFIG_AM335X_USB1_MODE,
234 .config = &musb_config,
236 .platform_ops = &musb_dsps_ops,
237 .board_data = &otg1_board_data,
241 int arch_misc_init(void)
243 #ifdef CONFIG_AM335X_USB0
244 musb_register(&otg0_plat, &otg0_board_data,
245 (void *)USB0_OTG_BASE);
247 #ifdef CONFIG_AM335X_USB1
248 musb_register(&otg1_plat, &otg1_board_data,
249 (void *)USB1_OTG_BASE);
254 #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
256 int arch_misc_init(void)
261 ret = uclass_first_device(UCLASS_MISC, &dev);
265 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
266 ret = usb_ether_init();
268 pr_err("USB ether init failed\n");
276 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
278 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
280 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
281 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
282 static void rtc32k_unlock(struct davinci_rtc *rtc)
285 * Unlock the RTC's registers. For more details please see the
286 * RTC_SS section of the TRM. In order to unlock we need to
287 * write these specific values (keys) in this order.
289 writel(RTC_KICK0R_WE, &rtc->kick0r);
290 writel(RTC_KICK1R_WE, &rtc->kick1r);
294 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
296 * Write contents of the RTC_SCRATCH1 register based on board type
297 * Two things are passed
298 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
299 * control gets to kernel, kernel reads the scratchpad register and gets to
300 * know that bootloader has rtc_only support.
302 * Second important thing is the board type (16:31). This is needed in the
303 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
304 * identify the board type and we go ahead and copy the board strings to
307 void update_rtc_magic(void)
309 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
310 u32 magic = RTC_MAGIC_VAL;
312 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
317 writel(magic, &rtc->scratch1);
322 * In the case of non-SPL based booting we'll want to call these
323 * functions a tiny bit later as it will require gd to be set and cleared
324 * and that's not true in s_init in this case so we cannot do it there.
326 int board_early_init_f(void)
330 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
337 * This function is the place to do per-board things such as ramp up the
338 * MPU clock frequency.
340 __weak void am33xx_spl_board_init(void)
344 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
345 static void rtc32k_enable(void)
347 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
351 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
352 writel((1 << 3) | (1 << 6), &rtc->osc);
356 static void uart_soft_reset(void)
358 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
361 regval = readl(&uart_base->uartsyscfg);
362 regval |= UART_RESET;
363 writel(regval, &uart_base->uartsyscfg);
364 while ((readl(&uart_base->uartsyssts) &
365 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
368 /* Disable smart idle */
369 regval = readl(&uart_base->uartsyscfg);
370 regval |= UART_SMART_IDLE_EN;
371 writel(regval, &uart_base->uartsyscfg);
374 static void watchdog_disable(void)
376 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
378 writel(0xAAAA, &wdtimer->wdtwspr);
379 while (readl(&wdtimer->wdtwwps) != 0x0)
381 writel(0x5555, &wdtimer->wdtwspr);
382 while (readl(&wdtimer->wdtwwps) != 0x0)
386 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
388 * Check if we are executing rtc-only + DDR mode, and resume from it if needed
390 static void rtc_only(void)
392 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
393 struct prm_device_inst *prm_device =
394 (struct prm_device_inst *)PRM_DEVICE_INST;
397 void (*resume_func)(void);
399 scratch1 = readl(&rtc->scratch1);
402 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
403 * written to this register when we want to wake up from RTC only
404 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
405 * bits 0-15: RTC_MAGIC_VAL
406 * bits 16-31: board type (needed for sdram_init)
408 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
413 /* Clear RTC magic */
414 writel(0, &rtc->scratch1);
417 * Update board type based on value stored on RTC_SCRATCH1, this
418 * is done so that we don't need to read the board type from eeprom
419 * over i2c bus which is expensive
421 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
424 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
425 * are resuming from self-refresh. This avoids an unnecessary re-init
426 * of the DDR. The re-init takes time and we would need to wait for
427 * it to complete before accessing DDR to avoid L3 NOC errors.
429 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
431 rtc_only_prcm_init();
434 /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */
435 writel(0, &prm_device->emif_ctrl);
437 resume_func = (void *)readl(&rtc->scratch0);
445 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
450 void early_system_init(void)
453 * The ROM will only have set up sufficient pinmux to allow for the
454 * first 4KiB NOR to be read, we must finish doing what we know of
455 * the NOR mux in this space in order to continue.
457 #ifdef CONFIG_NOR_BOOT
458 enable_norboot_pin_mux();
462 setup_early_clocks();
464 #ifdef CONFIG_SPL_BUILD
466 * Save the boot parameters passed from romcode.
467 * We cannot delay the saving further than this,
468 * to prevent overwrites.
470 save_omap_boot_params();
472 #ifdef CONFIG_DEBUG_UART_OMAP
475 #ifdef CONFIG_TI_I2C_BOARD_DETECT
478 #ifdef CONFIG_SPL_BUILD
481 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
482 /* Enable RTC32K clock */
487 #ifdef CONFIG_SPL_BUILD
488 void board_init_f(ulong dummy)
492 board_early_init_f();
494 /* dram_init must store complete ramsize in gd->ram_size */
495 gd->ram_size = get_ram_size(
496 (void *)CONFIG_SYS_SDRAM_BASE,
497 CONFIG_MAX_RAM_BANK_SIZE);
503 int arch_cpu_init_dm(void)
506 #ifndef CONFIG_SKIP_LOWLEVEL_INIT