2 * (C) Copyright 2009 Alessandro Rubini
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/mtu.h>
12 * The timer is a decrementer, we'll left it free running at 2.4MHz.
13 * We have 2.4 ticks per microsecond and an overflow in almost 30min
15 #define TIMER_CLOCK (24 * 100 * 1000)
16 #define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
17 #define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
18 #define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
19 #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
21 /* macro to read the decrementing 32 bit timer as an increasing count */
22 #define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
24 /* Configure a free-running, auto-wrap counter with no prescaler */
29 writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
30 CONFIG_SYS_TIMERBASE + MTU_CR(0));
33 writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
35 * The load-register isn't really immediate: it changes on clock
36 * edges, so we must wait for our newly-written value to appear.
37 * Since we might miss reading 0, wait for any change in value.
40 while (READ_TIMER() == val)
46 /* Return how many HZ passed since "base" */
47 ulong get_timer(ulong base)
49 return TICKS_TO_HZ(READ_TIMER()) - base;
52 /* Delay x useconds */
53 void __udelay(unsigned long usec)
58 end = ini + USEC_TO_COUNT(usec);
59 while ((signed)(end - READ_TIMER()) > 0)
63 unsigned long long get_ticks(void)