1 // SPDX-License-Identifier: GPL-2.0
3 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
4 * 370/XP, Dove, Orion5x and MV78xx0)
6 * Ported from the Barebox version to U-Boot by:
7 * Stefan Roese <sr@denx.de>
9 * The Barebox version is:
10 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
12 * based on mbus driver from Linux
13 * (C) Copyright 2008 Marvell Semiconductor
15 * The Marvell EBU SoCs have a configurable physical address space:
16 * the physical address at which certain devices (PCIe, NOR, NAND,
17 * etc.) sit can be configured. The configuration takes place through
18 * two sets of registers:
20 * - One to configure the access of the CPU to the devices. Depending
21 * on the families, there are between 8 and 20 configurable windows,
22 * each can be use to create a physical memory window that maps to a
23 * specific device. Devices are identified by a tuple (target,
26 * - One to configure the access to the CPU to the SDRAM. There are
27 * either 2 (for Dove) or 4 (for other families) windows to map the
28 * SDRAM into the physical address space.
32 * - Reads out the SDRAM address decoding windows at initialization
33 * time, and fills the mbus_dram_info structure with these
34 * informations. The exported function mv_mbus_dram_info() allow
35 * device drivers to get those informations related to the SDRAM
36 * address decoding windows. This is because devices also have their
37 * own windows (configured through registers that are part of each
38 * device register space), and therefore the drivers for Marvell
39 * devices have to configure those device -> SDRAM windows to ensure
40 * that DMA works properly.
42 * - Provides an API for platform code or device drivers to
43 * dynamically add or remove address decoding windows for the CPU ->
44 * device accesses. This API is mvebu_mbus_add_window_by_id(),
45 * mvebu_mbus_add_window_remap_by_id() and
46 * mvebu_mbus_del_window().
51 #include <linux/errno.h>
53 #include <asm/arch/cpu.h>
54 #include <asm/arch/soc.h>
55 #include <linux/log2.h>
56 #include <linux/mbus.h>
58 /* DDR target is the same on all platforms */
61 /* CPU Address Decode Windows registers */
62 #define WIN_CTRL_OFF 0x0000
63 #define WIN_CTRL_ENABLE BIT(0)
64 #define WIN_CTRL_TGT_MASK 0xf0
65 #define WIN_CTRL_TGT_SHIFT 4
66 #define WIN_CTRL_ATTR_MASK 0xff00
67 #define WIN_CTRL_ATTR_SHIFT 8
68 #define WIN_CTRL_SIZE_MASK 0xffff0000
69 #define WIN_CTRL_SIZE_SHIFT 16
70 #define WIN_BASE_OFF 0x0004
71 #define WIN_BASE_LOW 0xffff0000
72 #define WIN_BASE_HIGH 0xf
73 #define WIN_REMAP_LO_OFF 0x0008
74 #define WIN_REMAP_LOW 0xffff0000
75 #define WIN_REMAP_HI_OFF 0x000c
77 #define ATTR_HW_COHERENCY (0x1 << 4)
79 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
80 #define DDR_BASE_CS_HIGH_MASK 0xf
81 #define DDR_BASE_CS_LOW_MASK 0xff000000
82 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
83 #define DDR_SIZE_ENABLED BIT(0)
84 #define DDR_SIZE_CS_MASK 0x1c
85 #define DDR_SIZE_CS_SHIFT 2
86 #define DDR_SIZE_MASK 0xff000000
88 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
90 struct mvebu_mbus_state;
92 struct mvebu_mbus_soc_data {
93 unsigned int num_wins;
94 unsigned int num_remappable_wins;
95 unsigned int (*win_cfg_offset)(const int win);
96 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
99 struct mvebu_mbus_state mbus_state
100 __attribute__ ((section(".data")));
101 static struct mbus_dram_target_info mbus_dram_info
102 __attribute__ ((section(".data")));
105 * Functions to manipulate the address decoding windows
108 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
109 int win, int *enabled, u64 *base,
110 u32 *size, u8 *target, u8 *attr,
113 void __iomem *addr = mbus->mbuswins_base +
114 mbus->soc->win_cfg_offset(win);
115 u32 basereg = readl(addr + WIN_BASE_OFF);
116 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
118 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
124 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
125 *base |= (basereg & WIN_BASE_LOW);
126 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
129 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
132 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
135 if (win < mbus->soc->num_remappable_wins) {
136 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
137 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
138 *remap = ((u64)remap_hi << 32) | remap_low;
145 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
150 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
152 writel(0, addr + WIN_BASE_OFF);
153 writel(0, addr + WIN_CTRL_OFF);
154 if (win < mbus->soc->num_remappable_wins) {
155 writel(0, addr + WIN_REMAP_LO_OFF);
156 writel(0, addr + WIN_REMAP_HI_OFF);
160 /* Checks whether the given window number is available */
161 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
164 void __iomem *addr = mbus->mbuswins_base +
165 mbus->soc->win_cfg_offset(win);
166 u32 ctrl = readl(addr + WIN_CTRL_OFF);
167 return !(ctrl & WIN_CTRL_ENABLE);
171 * Checks whether the given (base, base+size) area doesn't overlap an
174 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
175 phys_addr_t base, size_t size,
178 u64 end = (u64)base + size;
181 for (win = 0; win < mbus->soc->num_wins; win++) {
187 mvebu_mbus_read_window(mbus, win,
188 &enabled, &wbase, &wsize,
189 &wtarget, &wattr, NULL);
194 wend = wbase + wsize;
197 * Check if the current window overlaps with the
198 * proposed physical range
200 if ((u64)base < wend && end > wbase)
204 * Check if target/attribute conflicts
206 if (target == wtarget && attr == wattr)
213 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
214 phys_addr_t base, size_t size)
218 for (win = 0; win < mbus->soc->num_wins; win++) {
223 mvebu_mbus_read_window(mbus, win,
224 &enabled, &wbase, &wsize,
230 if (base == wbase && size == wsize)
237 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
238 int win, phys_addr_t base, size_t size,
239 phys_addr_t remap, u8 target,
242 void __iomem *addr = mbus->mbuswins_base +
243 mbus->soc->win_cfg_offset(win);
244 u32 ctrl, remap_addr;
246 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
247 (attr << WIN_CTRL_ATTR_SHIFT) |
248 (target << WIN_CTRL_TGT_SHIFT) |
251 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
252 writel(ctrl, addr + WIN_CTRL_OFF);
253 if (win < mbus->soc->num_remappable_wins) {
254 if (remap == MVEBU_MBUS_NO_REMAP)
258 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
259 writel(0, addr + WIN_REMAP_HI_OFF);
265 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
266 phys_addr_t base, size_t size,
267 phys_addr_t remap, u8 target,
272 if (remap == MVEBU_MBUS_NO_REMAP) {
273 for (win = mbus->soc->num_remappable_wins;
274 win < mbus->soc->num_wins; win++)
275 if (mvebu_mbus_window_is_free(mbus, win))
276 return mvebu_mbus_setup_window(mbus, win, base,
282 for (win = 0; win < mbus->soc->num_wins; win++)
283 if (mvebu_mbus_window_is_free(mbus, win))
284 return mvebu_mbus_setup_window(mbus, win, base, size,
285 remap, target, attr);
291 * SoC-specific functions and definitions
294 static unsigned int armada_370_xp_mbus_win_offset(int win)
296 /* The register layout is a bit annoying and the below code
297 * tries to cope with it.
298 * - At offset 0x0, there are the registers for the first 8
299 * windows, with 4 registers of 32 bits per window (ctrl,
300 * base, remap low, remap high)
301 * - Then at offset 0x80, there is a hole of 0x10 bytes for
302 * the internal registers base address and internal units
303 * sync barrier register.
304 * - Then at offset 0x90, there the registers for 12
305 * windows, with only 2 registers of 32 bits per window
311 return 0x90 + ((win - 8) << 3);
314 static unsigned int orion5x_mbus_win_offset(int win)
319 static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
324 mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
326 for (i = 0, cs = 0; i < 4; i++) {
327 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
328 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
331 * We only take care of entries for which the chip
332 * select is enabled, and that don't have high base
333 * address bits set (devices can only access the first
334 * 32 bits of the memory).
336 if ((size & DDR_SIZE_ENABLED) &&
337 !(base & DDR_BASE_CS_HIGH_MASK)) {
338 struct mbus_dram_window *w;
340 w = &mbus_dram_info.cs[cs++];
342 w->mbus_attr = 0xf & ~(1 << i);
343 w->base = base & DDR_BASE_CS_LOW_MASK;
344 w->size = (size | ~DDR_SIZE_MASK) + 1;
347 mbus_dram_info.num_cs = cs;
349 #if defined(CONFIG_ARMADA_MSYS)
350 /* Disable MBUS Err Prop - in order to avoid data aborts */
351 clrbits_le32(mbus->mbuswins_base + 0x200, BIT(8));
355 static const struct mvebu_mbus_soc_data
356 armada_370_xp_mbus_data __maybe_unused = {
358 .num_remappable_wins = 8,
359 .win_cfg_offset = armada_370_xp_mbus_win_offset,
360 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
363 static const struct mvebu_mbus_soc_data
364 kirkwood_mbus_data __maybe_unused = {
366 .num_remappable_wins = 4,
367 .win_cfg_offset = orion5x_mbus_win_offset,
368 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
372 * Public API of the driver
374 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
376 return &mbus_dram_info;
379 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
380 unsigned int attribute,
381 phys_addr_t base, size_t size,
384 struct mvebu_mbus_state *s = &mbus_state;
386 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
387 printf("Cannot add window '%x:%x', conflicts with another window\n",
392 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
395 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
396 phys_addr_t base, size_t size)
398 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
399 size, MVEBU_MBUS_NO_REMAP);
402 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
406 win = mvebu_mbus_find_window(&mbus_state, base, size);
410 mvebu_mbus_disable_window(&mbus_state, win);
414 #ifndef CONFIG_ARCH_KIRKWOOD
415 static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus,
421 for (win = 0; win < mbus->soc->num_wins; win++) {
427 mvebu_mbus_read_window(mbus, win,
428 &enabled, &wbase, &wsize,
429 &wtarget, &wattr, NULL);
439 static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus)
445 /* Set MBUS bridge base/ctrl */
446 mvebu_mbus_get_lowest_base(&mbus_state, &base);
448 size = 0xffffffff - base + 1;
449 if (!is_power_of_2(size)) {
450 /* Round up to next power of 2 */
451 size = 1 << (ffs(base) + 1);
452 base = 0xffffffff - size + 1;
455 /* Now write base and size */
456 writel(base, MBUS_BRIDGE_WIN_BASE_REG);
457 /* Align window size to 64KiB */
458 val = (size / (64 << 10)) - 1;
459 writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG);
463 int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
464 u32 base, u32 size, u8 target, u8 attr)
466 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
467 printf("Cannot add window '%04x:%04x', conflicts with another window\n",
473 * In U-Boot we first try to add the mbus window to the remap windows.
474 * If this fails, lets try to add the windows to the non-remap windows.
476 if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
477 if (mvebu_mbus_alloc_window(mbus, base, size,
478 MVEBU_MBUS_NO_REMAP, target, attr))
482 #ifndef CONFIG_ARCH_KIRKWOOD
484 * Re-configure the mbus bridge registers each time this function
485 * is called. Since it may get called from the board code in
486 * later boot stages as well.
488 mvebu_config_mbus_bridge(mbus);
494 int mvebu_mbus_probe(struct mbus_win windows[], int count)
500 #if defined(CONFIG_ARCH_KIRKWOOD)
501 mbus_state.soc = &kirkwood_mbus_data;
503 #if defined(CONFIG_ARCH_MVEBU)
504 mbus_state.soc = &armada_370_xp_mbus_data;
507 mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
508 mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
510 for (win = 0; win < mbus_state.soc->num_wins; win++)
511 mvebu_mbus_disable_window(&mbus_state, win);
513 mbus_state.soc->setup_cpu_target(&mbus_state);
515 /* Setup statically declared windows in the DT */
516 for (i = 0; i < count; i++) {
520 target = windows[i].target;
521 attr = windows[i].attr;
522 base = windows[i].base;
523 size = windows[i].size;
524 ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);