1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 * Header file for the Marvell's Feroceon CPU core.
14 #include <linux/bitops.h>
17 #define SOC_MV78230_ID 0x7823
18 #define SOC_MV78260_ID 0x7826
19 #define SOC_MV78460_ID 0x7846
20 #define SOC_88F6720_ID 0x6720
21 #define SOC_88F6810_ID 0x6810
22 #define SOC_88F6820_ID 0x6820
23 #define SOC_88F6828_ID 0x6828
24 #define SOC_98DX3236_ID 0xf410
25 #define SOC_98DX3336_ID 0xf400
26 #define SOC_98DX4251_ID 0xfc00
29 #define MV_88F67XX_A0_ID 0x3
32 #define MV_88F68XX_Z1_ID 0x0
33 #define MV_88F68XX_A0_ID 0x4
34 #define MV_88F68XX_B0_ID 0xa
36 /* TCLK Core Clock definition */
37 #ifndef CONFIG_SYS_TCLK
38 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
41 /* SOC specific definations */
42 #define INTREG_BASE 0xd0000000
43 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
44 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700)
46 * The SPL U-Boot version still runs with the default
47 * address for the internal registers, configured by
48 * the BootROM. Only the main U-Boot version uses the
49 * new internal register base address, that also is
50 * required for the Linux kernel.
52 #define SOC_REGS_PHY_BASE 0xd0000000
53 #elif defined(CONFIG_ARMADA_8K)
54 #define SOC_REGS_PHY_BASE 0xf0000000
56 #define SOC_REGS_PHY_BASE 0xf1000000
58 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
60 #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
61 #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
62 #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
63 #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
64 #define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100))
65 #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
66 #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
67 #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
68 #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
69 #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
70 #define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700))
71 #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
72 #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
73 #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
74 #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
75 #define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000))
76 #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000))
77 #define MVEBU_REG_PCIE0_BASE (MVEBU_REGISTER(0x80000))
78 #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
79 #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
80 #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
81 #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
82 #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
83 #ifdef CONFIG_ARMADA_MSYS
84 #define MVEBU_DFX_BASE (MBUS_DFX_BASE)
86 #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
89 #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
90 #define MBUS_ERR_PROP_EN (1 << 8)
92 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
93 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
95 #define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08)
96 #define NAND_EN BIT(0)
97 #define NAND_ARBITER_EN BIT(27)
99 #define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c)
100 #define GE0_PUP_EN BIT(0)
101 #define GE1_PUP_EN BIT(1)
102 #define LCD_PUP_EN BIT(2)
103 #define NAND_PUP_EN BIT(4)
104 #define SPI_PUP_EN BIT(5)
106 #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
107 #ifdef CONFIG_ARMADA_MSYS
108 #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
109 #define NAND_ECC_DIVCKL_RATIO_OFFS 6
110 #define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
112 #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
114 #ifdef CONFIG_ARMADA_MSYS
115 #define NAND_ECC_DIVCKL_RATIO_OFFS 6
116 #define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
118 #define NAND_ECC_DIVCKL_RATIO_OFFS 8
119 #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
122 #define SDRAM_MAX_CS 4
123 #define SDRAM_ADDR_MASK 0xFF000000
125 /* MVEBU CPU memory windows */
126 #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
127 #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
128 #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
130 #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
132 /* BootROM error register (also includes some status infos) */
133 #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
134 #define BOOTROM_ERR_MODE_OFFS 28
135 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
136 #define BOOTROM_ERR_MODE_UART 0x6
137 #define BOOTROM_ERR_CODE_OFFS 0
138 #define BOOTROM_ERR_CODE_MASK (0xf << BOOTROM_ERR_CODE_OFFS)
140 #if defined(CONFIG_ARMADA_375)
141 /* SAR values for Armada 375 */
142 #define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200))
143 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204))
145 #define SAR_CPU_FREQ_OFFS 17
146 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
148 #define BOOT_DEV_SEL_OFFS 3
149 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
151 #define BOOT_FROM_UART 0x30
152 #define BOOT_FROM_SPI 0x38
153 #elif defined(CONFIG_ARMADA_38X)
154 /* SAR values for Armada 38x */
155 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
157 #define SAR_CPU_FREQ_OFFS 10
158 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
159 #define SAR_BOOT_DEVICE_OFFS 4
160 #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
162 #define BOOT_DEV_SEL_OFFS 4
163 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
165 #define BOOT_FROM_NAND 0x0A
166 #define BOOT_FROM_SATA 0x22
167 #define BOOT_FROM_UART 0x28
168 #define BOOT_FROM_SATA_ALT 0x2A
169 #define BOOT_FROM_UART_ALT 0x3f
170 #define BOOT_FROM_SPI 0x32
171 #define BOOT_FROM_MMC 0x30
172 #define BOOT_FROM_MMC_ALT 0x31
173 #elif defined(CONFIG_ARMADA_MSYS)
174 /* SAR values for MSYS */
175 #define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
176 #define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
178 #define SAR_CPU_FREQ_OFFS 18
179 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
180 #define SAR_BOOT_DEVICE_OFFS 11
181 #define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
183 #define BOOT_DEV_SEL_OFFS 11
184 #define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
186 #define BOOT_FROM_NAND 0x1
187 #define BOOT_FROM_UART 0x2
188 #define BOOT_FROM_SPI 0x3
190 /* SAR values for Armada XP */
191 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
192 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
194 #define SAR_CPU_FREQ_OFFS 21
195 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
196 #define SAR_FFC_FREQ_OFFS 24
197 #define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS)
198 #define SAR2_CPU_FREQ_OFFS 20
199 #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
200 #define SAR_BOOT_DEVICE_OFFS 5
201 #define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
203 #define BOOT_DEV_SEL_OFFS 5
204 #define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS)
206 #define BOOT_FROM_UART 0x2
207 #define BOOT_FROM_SPI 0x3
210 #endif /* _MVEBU_SOC_H */