2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/mbus.h>
11 #include <asm/pl310.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
16 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
17 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
19 static struct mbus_win windows[] = {
21 { MBUS_SPI_BASE, MBUS_SPI_SIZE,
22 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
25 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
29 void lowlevel_init(void)
32 * Dummy implementation, we only need LOWLEVEL_INIT
33 * on Armada to configure CP15 in start.S / cpu_init_cp15()
37 void reset_cpu(unsigned long ignored)
39 struct mvebu_system_registers *reg =
40 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
42 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
43 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
48 int mvebu_soc_family(void)
50 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
52 if ((devid == SOC_MV78260_ID) || (devid == SOC_MV78460_ID))
55 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
56 devid == SOC_88F6828_ID)
57 return MVEBU_SOC_A38X;
59 return MVEBU_SOC_UNKNOWN;
62 #if defined(CONFIG_DISPLAY_CPUINFO)
64 #if defined(CONFIG_ARMADA_38X)
65 /* SAR values for Armada 38x */
66 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
67 #define SAR_CPU_FREQ_OFFS 10
68 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
70 struct sar_freq_modes sar_freq_tab[] = {
71 { 0x0, 0x0, 666, 333, 333 },
72 { 0x2, 0x0, 800, 400, 400 },
73 { 0x4, 0x0, 1066, 533, 533 },
74 { 0x6, 0x0, 1200, 600, 600 },
75 { 0x8, 0x0, 1332, 666, 666 },
76 { 0xc, 0x0, 1600, 800, 800 },
77 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
80 /* SAR values for Armada XP */
81 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
82 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
83 #define SAR_CPU_FREQ_OFFS 21
84 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
85 #define SAR_FFC_FREQ_OFFS 24
86 #define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS)
87 #define SAR2_CPU_FREQ_OFFS 20
88 #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
90 struct sar_freq_modes sar_freq_tab[] = {
91 { 0xa, 0x5, 800, 400, 400 },
92 { 0x1, 0x5, 1066, 533, 533 },
93 { 0x2, 0x5, 1200, 600, 600 },
94 { 0x2, 0x9, 1200, 600, 400 },
95 { 0x3, 0x5, 1333, 667, 667 },
96 { 0x4, 0x5, 1500, 750, 750 },
97 { 0x4, 0x9, 1500, 750, 500 },
98 { 0xb, 0x9, 1600, 800, 533 },
99 { 0xb, 0xa, 1600, 800, 640 },
100 { 0xb, 0x5, 1600, 800, 800 },
101 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
105 void get_sar_freq(struct sar_freq_modes *sar_freq)
111 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
112 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
113 #if !defined(CONFIG_ARMADA_38X)
115 * Shift CPU0 clock frequency select bit from SAR2 register
116 * into correct position
118 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
119 >> SAR2_CPU_FREQ_OFFS) << 3;
121 for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
122 if (sar_freq_tab[i].val == freq) {
123 #if defined(CONFIG_ARMADA_38X)
124 *sar_freq = sar_freq_tab[i];
130 ffc = (val & SAR_FFC_FREQ_MASK) >>
132 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
133 if (sar_freq_tab[k].ffc == ffc) {
134 *sar_freq = sar_freq_tab[k];
143 /* SAR value not found, return 0 for frequencies */
144 *sar_freq = sar_freq_tab[i - 1];
147 int print_cpuinfo(void)
149 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
150 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
151 struct sar_freq_modes sar_freq;
176 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
185 printf("?? (%x)", revid);
190 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
192 case MV_88F68XX_Z1_ID:
195 case MV_88F68XX_A0_ID:
199 printf("?? (%x)", revid);
204 get_sar_freq(&sar_freq);
205 printf(" at %d MHz\n", sar_freq.p_clk);
209 #endif /* CONFIG_DISPLAY_CPUINFO */
212 * This function initialize Controller DRAM Fastpath windows.
213 * It takes the CS size information from the 0x1500 scratch registers
214 * and sets the correct windows sizes and base addresses accordingly.
216 * These values are set in the scratch registers by the Marvell
217 * DDR3 training code, which is executed by the BootROM before the
218 * main payload (U-Boot) is executed. This training code is currently
219 * only available in the Marvell U-Boot version. It needs to be
220 * ported to mainline U-Boot SPL at some point.
222 static void update_sdram_window_sizes(void)
228 for (i = 0; i < SDRAM_MAX_CS; i++) {
229 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
231 size |= ~(SDRAM_ADDR_MASK);
233 /* Set Base Address */
234 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
235 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
238 * Check if out of max window size and resize
241 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
242 ~(SDRAM_ADDR_MASK)) | 1;
243 temp |= (size & SDRAM_ADDR_MASK);
244 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
246 base += ((u64)size + 1);
249 * Disable window if not used, otherwise this
250 * leads to overlapping enabled windows with
251 * pretty strange results
253 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
258 void mmu_disable(void)
261 "mrc p15, 0, r0, c1, c0, 0\n"
263 "mcr p15, 0, r0, c1, c0, 0\n");
266 #ifdef CONFIG_ARCH_CPU_INIT
267 static void set_cbar(u32 addr)
269 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
272 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
273 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
274 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
275 (((addr) & 0xF) << 6))
276 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
277 (((reg) & 0xF) << 2))
279 static void setup_usb_phys(void)
287 /* Setup PLL frequency */
288 /* USB REF frequency = 25 MHz */
289 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
291 /* Power up PLL and PHY channel */
292 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
294 /* Assert VCOCAL_START */
295 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
300 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
303 for (dev = 0; dev < 3; dev++) {
304 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
306 /* Assert REG_RCAL_START in channel REG 1 */
307 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
309 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
314 * This function is not called from the SPL U-Boot version
316 int arch_cpu_init(void)
318 struct pl310_regs *const pl310 =
319 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
322 * Only with disabled MMU its possible to switch the base
323 * register address on Armada 38x. Without this the SDRAM
324 * located at >= 0x4000.0000 is also not accessible, as its
325 * still locked to cache.
329 /* Linux expects the internal registers to be at 0xf1000000 */
330 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
331 set_cbar(SOC_REGS_PHY_BASE + 0xC000);
334 * From this stage on, the SoC detection is working. As we have
335 * configured the internal register base to the value used
336 * in the macros / defines in the U-Boot header (soc.h).
339 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
341 * To fully release / unlock this area from cache, we need
342 * to flush all caches and disable the L2 cache.
346 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
350 * We need to call mvebu_mbus_probe() before calling
351 * update_sdram_window_sizes() as it disables all previously
352 * configured mbus windows and then configures them as
353 * required for U-Boot. Calling update_sdram_window_sizes()
354 * without this configuration will not work, as the internal
355 * registers can't be accessed reliably because of potenial
357 * After updating the SDRAM access windows we need to call
358 * mvebu_mbus_probe() again, as this now correctly configures
359 * the SDRAM areas that are later used by the MVEBU drivers
364 * First disable all windows
366 mvebu_mbus_probe(NULL, 0);
368 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
370 * Now the SDRAM access windows can be reconfigured using
371 * the information in the SDRAM scratch pad registers
373 update_sdram_window_sizes();
377 * Finally the mbus windows can be configured with the
378 * updated SDRAM sizes
380 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
382 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
383 /* Enable GBE0, GBE1, LCD and NFC PUP */
384 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
385 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
386 NAND_PUP_EN | SPI_PUP_EN);
388 /* Configure USB PLL and PHYs on AXP */
392 /* Enable NAND and NAND arbiter */
393 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
395 /* Disable MBUS error propagation */
396 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
400 #endif /* CONFIG_ARCH_CPU_INIT */
402 u32 mvebu_get_nand_clock(void)
404 return CONFIG_SYS_MVEBU_PLL_CLOCK /
405 ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
406 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
410 * SOC specific misc init
412 #if defined(CONFIG_ARCH_MISC_INIT)
413 int arch_misc_init(void)
415 /* Nothing yet, perhaps we need something here later */
418 #endif /* CONFIG_ARCH_MISC_INIT */
420 #ifdef CONFIG_MV_SDHCI
421 int board_mmc_init(bd_t *bis)
423 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
424 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
430 #ifdef CONFIG_SCSI_AHCI_PLAT
431 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
432 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
434 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
435 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
436 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
438 static void ahci_mvebu_mbus_config(void __iomem *base)
440 const struct mbus_dram_target_info *dram;
443 dram = mvebu_mbus_dram_info();
445 for (i = 0; i < 4; i++) {
446 writel(0, base + AHCI_WINDOW_CTRL(i));
447 writel(0, base + AHCI_WINDOW_BASE(i));
448 writel(0, base + AHCI_WINDOW_SIZE(i));
451 for (i = 0; i < dram->num_cs; i++) {
452 const struct mbus_dram_window *cs = dram->cs + i;
454 writel((cs->mbus_attr << 8) |
455 (dram->mbus_dram_target_id << 4) | 1,
456 base + AHCI_WINDOW_CTRL(i));
457 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
458 writel(((cs->size - 1) & 0xffff0000),
459 base + AHCI_WINDOW_SIZE(i));
463 static void ahci_mvebu_regret_option(void __iomem *base)
466 * Enable the regret bit to allow the SATA unit to regret a
467 * request that didn't receive an acknowlegde and avoid a
470 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
471 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
476 printf("MVEBU SATA INIT\n");
477 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
478 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
479 ahci_init((void __iomem *)MVEBU_SATA0_BASE);
483 void enable_caches(void)
485 /* Avoid problem with e.g. neta ethernet driver */
486 invalidate_dcache_all();
488 /* Enable D-cache. I-cache is already enabled in start.S */
492 void v7_outer_cache_enable(void)
494 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
495 struct pl310_regs *const pl310 =
496 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
499 /* The L2 cache is already disabled at this point */
502 * For Aurora cache in no outer mode, enable via the CP15
503 * coprocessor broadcasting of cache commands to L2.
505 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
506 u |= BIT(8); /* Set the FW bit */
507 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
511 /* Enable the L2 cache */
512 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
516 void v7_outer_cache_disable(void)
518 struct pl310_regs *const pl310 =
519 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
521 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);