2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/mbus.h>
12 #include <asm/pl310.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
17 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
18 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
20 static struct mbus_win windows[] = {
21 /* PCIE MEM address space */
22 { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
24 /* PCIE IO address space */
25 { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
28 { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
32 { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
36 void reset_cpu(unsigned long ignored)
38 struct mvebu_system_registers *reg =
39 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
41 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
42 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
47 int mvebu_soc_family(void)
49 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
51 if (devid == SOC_MV78460_ID)
54 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
55 devid == SOC_88F6828_ID)
56 return MVEBU_SOC_A38X;
58 return MVEBU_SOC_UNKNOWN;
61 #if defined(CONFIG_DISPLAY_CPUINFO)
62 int print_cpuinfo(void)
64 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
65 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
87 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
96 printf("?? (%x)\n", revid);
101 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
103 case MV_88F68XX_Z1_ID:
106 case MV_88F68XX_A0_ID:
110 printf("?? (%x)\n", revid);
117 #endif /* CONFIG_DISPLAY_CPUINFO */
120 * This function initialize Controller DRAM Fastpath windows.
121 * It takes the CS size information from the 0x1500 scratch registers
122 * and sets the correct windows sizes and base addresses accordingly.
124 * These values are set in the scratch registers by the Marvell
125 * DDR3 training code, which is executed by the BootROM before the
126 * main payload (U-Boot) is executed. This training code is currently
127 * only available in the Marvell U-Boot version. It needs to be
128 * ported to mainline U-Boot SPL at some point.
130 static void update_sdram_window_sizes(void)
136 for (i = 0; i < SDRAM_MAX_CS; i++) {
137 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
139 size |= ~(SDRAM_ADDR_MASK);
141 /* Set Base Address */
142 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
143 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
146 * Check if out of max window size and resize
149 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
150 ~(SDRAM_ADDR_MASK)) | 1;
151 temp |= (size & SDRAM_ADDR_MASK);
152 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
154 base += ((u64)size + 1);
157 * Disable window if not used, otherwise this
158 * leads to overlapping enabled windows with
159 * pretty strange results
161 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
166 #ifdef CONFIG_ARCH_CPU_INIT
167 static void set_cbar(u32 addr)
169 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
173 int arch_cpu_init(void)
175 /* Linux expects the internal registers to be at 0xf1000000 */
176 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
177 set_cbar(SOC_REGS_PHY_BASE + 0xC000);
180 * We need to call mvebu_mbus_probe() before calling
181 * update_sdram_window_sizes() as it disables all previously
182 * configured mbus windows and then configures them as
183 * required for U-Boot. Calling update_sdram_window_sizes()
184 * without this configuration will not work, as the internal
185 * registers can't be accessed reliably because of potenial
187 * After updating the SDRAM access windows we need to call
188 * mvebu_mbus_probe() again, as this now correctly configures
189 * the SDRAM areas that are later used by the MVEBU drivers
194 * First disable all windows
196 mvebu_mbus_probe(NULL, 0);
198 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
200 * Now the SDRAM access windows can be reconfigured using
201 * the information in the SDRAM scratch pad registers
203 update_sdram_window_sizes();
207 * Finally the mbus windows can be configured with the
208 * updated SDRAM sizes
210 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
214 #endif /* CONFIG_ARCH_CPU_INIT */
217 * SOC specific misc init
219 #if defined(CONFIG_ARCH_MISC_INIT)
220 int arch_misc_init(void)
222 /* Nothing yet, perhaps we need something here later */
225 #endif /* CONFIG_ARCH_MISC_INIT */
228 int cpu_eth_init(bd_t *bis)
230 u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
231 MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
232 u8 phy_addr[] = CONFIG_PHY_ADDR;
236 * Only Armada XP supports all 4 ethernet interfaces. A38x has
237 * slightly different base addresses for its 2-3 interfaces.
239 if (mvebu_soc_family() != MVEBU_SOC_AXP) {
240 enet_base[1] = MVEBU_EGIGA2_BASE;
241 enet_base[2] = MVEBU_EGIGA3_BASE;
244 for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
245 mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
251 #ifdef CONFIG_MV_SDHCI
252 int board_mmc_init(bd_t *bis)
254 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
255 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
261 #ifdef CONFIG_SCSI_AHCI_PLAT
262 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
263 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
265 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
266 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
267 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
269 static void ahci_mvebu_mbus_config(void __iomem *base)
271 const struct mbus_dram_target_info *dram;
274 dram = mvebu_mbus_dram_info();
276 for (i = 0; i < 4; i++) {
277 writel(0, base + AHCI_WINDOW_CTRL(i));
278 writel(0, base + AHCI_WINDOW_BASE(i));
279 writel(0, base + AHCI_WINDOW_SIZE(i));
282 for (i = 0; i < dram->num_cs; i++) {
283 const struct mbus_dram_window *cs = dram->cs + i;
285 writel((cs->mbus_attr << 8) |
286 (dram->mbus_dram_target_id << 4) | 1,
287 base + AHCI_WINDOW_CTRL(i));
288 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
289 writel(((cs->size - 1) & 0xffff0000),
290 base + AHCI_WINDOW_SIZE(i));
294 static void ahci_mvebu_regret_option(void __iomem *base)
297 * Enable the regret bit to allow the SATA unit to regret a
298 * request that didn't receive an acknowlegde and avoid a
301 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
302 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
307 printf("MVEBU SATA INIT\n");
308 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
309 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
310 ahci_init((void __iomem *)MVEBU_SATA0_BASE);
314 #ifndef CONFIG_SYS_DCACHE_OFF
315 void enable_caches(void)
317 struct pl310_regs *const pl310 =
318 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
320 /* First disable L2 cache - may still be enable from BootROM */
321 if (mvebu_soc_family() == MVEBU_SOC_A38X)
322 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
324 /* Avoid problem with e.g. neta ethernet driver */
325 invalidate_dcache_all();
327 /* Enable D-cache. I-cache is already enabled in start.S */