1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
8 #include <linux/mbus.h>
10 #include <asm/pl310.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
15 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
16 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
18 static struct mbus_win windows[] = {
20 { MBUS_SPI_BASE, MBUS_SPI_SIZE,
21 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
24 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
25 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
27 #ifdef CONFIG_ARMADA_MSYS
29 { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
33 void lowlevel_init(void)
36 * Dummy implementation, we only need LOWLEVEL_INIT
37 * on Armada to configure CP15 in start.S / cpu_init_cp15()
41 void reset_cpu(unsigned long ignored)
43 struct mvebu_system_registers *reg =
44 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
46 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
47 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
52 int mvebu_soc_family(void)
54 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
63 return MVEBU_SOC_A375;
68 return MVEBU_SOC_A38X;
73 return MVEBU_SOC_MSYS;
76 return MVEBU_SOC_UNKNOWN;
79 #if defined(CONFIG_DISPLAY_CPUINFO)
81 #if defined(CONFIG_ARMADA_375)
82 /* SAR frequency values for Armada 375 */
83 static const struct sar_freq_modes sar_freq_tab[] = {
84 { 0, 0x0, 266, 133, 266 },
85 { 1, 0x0, 333, 167, 167 },
86 { 2, 0x0, 333, 167, 222 },
87 { 3, 0x0, 333, 167, 333 },
88 { 4, 0x0, 400, 200, 200 },
89 { 5, 0x0, 400, 200, 267 },
90 { 6, 0x0, 400, 200, 400 },
91 { 7, 0x0, 500, 250, 250 },
92 { 8, 0x0, 500, 250, 334 },
93 { 9, 0x0, 500, 250, 500 },
94 { 10, 0x0, 533, 267, 267 },
95 { 11, 0x0, 533, 267, 356 },
96 { 12, 0x0, 533, 267, 533 },
97 { 13, 0x0, 600, 300, 300 },
98 { 14, 0x0, 600, 300, 400 },
99 { 15, 0x0, 600, 300, 600 },
100 { 16, 0x0, 666, 333, 333 },
101 { 17, 0x0, 666, 333, 444 },
102 { 18, 0x0, 666, 333, 666 },
103 { 19, 0x0, 800, 400, 267 },
104 { 20, 0x0, 800, 400, 400 },
105 { 21, 0x0, 800, 400, 534 },
106 { 22, 0x0, 900, 450, 300 },
107 { 23, 0x0, 900, 450, 450 },
108 { 24, 0x0, 900, 450, 600 },
109 { 25, 0x0, 1000, 500, 500 },
110 { 26, 0x0, 1000, 500, 667 },
111 { 27, 0x0, 1000, 333, 500 },
112 { 28, 0x0, 400, 400, 400 },
113 { 29, 0x0, 1100, 550, 550 },
114 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
116 #elif defined(CONFIG_ARMADA_38X)
117 /* SAR frequency values for Armada 38x */
118 static const struct sar_freq_modes sar_freq_tab[] = {
119 { 0x0, 0x0, 666, 333, 333 },
120 { 0x2, 0x0, 800, 400, 400 },
121 { 0x4, 0x0, 1066, 533, 533 },
122 { 0x6, 0x0, 1200, 600, 600 },
123 { 0x8, 0x0, 1332, 666, 666 },
124 { 0xc, 0x0, 1600, 800, 800 },
125 { 0x10, 0x0, 1866, 933, 933 },
126 { 0x13, 0x0, 2000, 1000, 933 },
127 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
129 #elif defined(CONFIG_ARMADA_MSYS)
130 static const struct sar_freq_modes sar_freq_tab[] = {
131 { 0x0, 0x0, 400, 400, 400 },
132 { 0x2, 0x0, 667, 333, 667 },
133 { 0x3, 0x0, 800, 400, 800 },
134 { 0x5, 0x0, 800, 400, 800 },
135 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
138 /* SAR frequency values for Armada XP */
139 static const struct sar_freq_modes sar_freq_tab[] = {
140 { 0xa, 0x5, 800, 400, 400 },
141 { 0x1, 0x5, 1066, 533, 533 },
142 { 0x2, 0x5, 1200, 600, 600 },
143 { 0x2, 0x9, 1200, 600, 400 },
144 { 0x3, 0x5, 1333, 667, 667 },
145 { 0x4, 0x5, 1500, 750, 750 },
146 { 0x4, 0x9, 1500, 750, 500 },
147 { 0xb, 0x9, 1600, 800, 533 },
148 { 0xb, 0xa, 1600, 800, 640 },
149 { 0xb, 0x5, 1600, 800, 800 },
150 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
154 void get_sar_freq(struct sar_freq_modes *sar_freq)
160 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
161 val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
163 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
165 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
166 #if defined(SAR2_CPU_FREQ_MASK)
168 * Shift CPU0 clock frequency select bit from SAR2 register
169 * into correct position
171 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
172 >> SAR2_CPU_FREQ_OFFS) << 3;
174 for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
175 if (sar_freq_tab[i].val == freq) {
176 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
177 *sar_freq = sar_freq_tab[i];
183 ffc = (val & SAR_FFC_FREQ_MASK) >>
185 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
186 if (sar_freq_tab[k].ffc == ffc) {
187 *sar_freq = sar_freq_tab[k];
196 /* SAR value not found, return 0 for frequencies */
197 *sar_freq = sar_freq_tab[i - 1];
200 int print_cpuinfo(void)
202 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
203 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
204 struct sar_freq_modes sar_freq;
230 case SOC_98DX3236_ID:
233 case SOC_98DX3336_ID:
236 case SOC_98DX4251_ID:
244 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
253 printf("?? (%x)", revid);
258 if (mvebu_soc_family() == MVEBU_SOC_A375) {
260 case MV_88F67XX_A0_ID:
264 printf("?? (%x)", revid);
269 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
271 case MV_88F68XX_Z1_ID:
274 case MV_88F68XX_A0_ID:
277 case MV_88F68XX_B0_ID:
281 printf("?? (%x)", revid);
286 if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
295 printf("?? (%x)", revid);
300 get_sar_freq(&sar_freq);
301 printf(" at %d MHz\n", sar_freq.p_clk);
305 #endif /* CONFIG_DISPLAY_CPUINFO */
308 * This function initialize Controller DRAM Fastpath windows.
309 * It takes the CS size information from the 0x1500 scratch registers
310 * and sets the correct windows sizes and base addresses accordingly.
312 * These values are set in the scratch registers by the Marvell
313 * DDR3 training code, which is executed by the SPL before the
314 * main payload (U-Boot) is executed.
316 static void update_sdram_window_sizes(void)
322 for (i = 0; i < SDRAM_MAX_CS; i++) {
323 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
325 size |= ~(SDRAM_ADDR_MASK);
327 /* Set Base Address */
328 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
329 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
332 * Check if out of max window size and resize
335 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
336 ~(SDRAM_ADDR_MASK)) | 1;
337 temp |= (size & SDRAM_ADDR_MASK);
338 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
340 base += ((u64)size + 1);
343 * Disable window if not used, otherwise this
344 * leads to overlapping enabled windows with
345 * pretty strange results
347 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
352 void mmu_disable(void)
355 "mrc p15, 0, r0, c1, c0, 0\n"
357 "mcr p15, 0, r0, c1, c0, 0\n");
360 #ifdef CONFIG_ARCH_CPU_INIT
361 static void set_cbar(u32 addr)
363 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
366 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
367 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
368 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
369 (((addr) & 0xF) << 6))
370 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
371 (((reg) & 0xF) << 2))
373 static void setup_usb_phys(void)
381 /* Setup PLL frequency */
382 /* USB REF frequency = 25 MHz */
383 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
385 /* Power up PLL and PHY channel */
386 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
388 /* Assert VCOCAL_START */
389 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
394 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
397 for (dev = 0; dev < 3; dev++) {
398 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
400 /* Assert REG_RCAL_START in channel REG 1 */
401 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
403 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
408 * This function is not called from the SPL U-Boot version
410 int arch_cpu_init(void)
412 struct pl310_regs *const pl310 =
413 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
416 * Only with disabled MMU its possible to switch the base
417 * register address on Armada 38x. Without this the SDRAM
418 * located at >= 0x4000.0000 is also not accessible, as its
419 * still locked to cache.
423 /* Linux expects the internal registers to be at 0xf1000000 */
424 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
425 set_cbar(SOC_REGS_PHY_BASE + 0xC000);
428 * From this stage on, the SoC detection is working. As we have
429 * configured the internal register base to the value used
430 * in the macros / defines in the U-Boot header (soc.h).
433 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
435 * To fully release / unlock this area from cache, we need
436 * to flush all caches and disable the L2 cache.
440 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
444 * We need to call mvebu_mbus_probe() before calling
445 * update_sdram_window_sizes() as it disables all previously
446 * configured mbus windows and then configures them as
447 * required for U-Boot. Calling update_sdram_window_sizes()
448 * without this configuration will not work, as the internal
449 * registers can't be accessed reliably because of potenial
451 * After updating the SDRAM access windows we need to call
452 * mvebu_mbus_probe() again, as this now correctly configures
453 * the SDRAM areas that are later used by the MVEBU drivers
458 * First disable all windows
460 mvebu_mbus_probe(NULL, 0);
462 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
464 * Now the SDRAM access windows can be reconfigured using
465 * the information in the SDRAM scratch pad registers
467 update_sdram_window_sizes();
471 * Finally the mbus windows can be configured with the
472 * updated SDRAM sizes
474 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
476 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
477 /* Enable GBE0, GBE1, LCD and NFC PUP */
478 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
479 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
480 NAND_PUP_EN | SPI_PUP_EN);
482 /* Configure USB PLL and PHYs on AXP */
486 /* Enable NAND and NAND arbiter */
487 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
489 /* Disable MBUS error propagation */
490 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
494 #endif /* CONFIG_ARCH_CPU_INIT */
496 u32 mvebu_get_nand_clock(void)
500 if (mvebu_soc_family() == MVEBU_SOC_A38X)
501 reg = MVEBU_DFX_DIV_CLK_CTRL(1);
502 else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
503 reg = MVEBU_DFX_DIV_CLK_CTRL(8);
505 reg = MVEBU_CORE_DIV_CLK_CTRL(1);
507 return CONFIG_SYS_MVEBU_PLL_CLOCK /
509 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
513 * SOC specific misc init
515 #if defined(CONFIG_ARCH_MISC_INIT)
516 int arch_misc_init(void)
518 /* Nothing yet, perhaps we need something here later */
521 #endif /* CONFIG_ARCH_MISC_INIT */
523 #ifdef CONFIG_MMC_SDHCI_MV
524 int board_mmc_init(bd_t *bis)
526 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
527 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
533 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
534 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
536 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
537 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
538 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
540 static void ahci_mvebu_mbus_config(void __iomem *base)
542 const struct mbus_dram_target_info *dram;
545 dram = mvebu_mbus_dram_info();
547 for (i = 0; i < 4; i++) {
548 writel(0, base + AHCI_WINDOW_CTRL(i));
549 writel(0, base + AHCI_WINDOW_BASE(i));
550 writel(0, base + AHCI_WINDOW_SIZE(i));
553 for (i = 0; i < dram->num_cs; i++) {
554 const struct mbus_dram_window *cs = dram->cs + i;
556 writel((cs->mbus_attr << 8) |
557 (dram->mbus_dram_target_id << 4) | 1,
558 base + AHCI_WINDOW_CTRL(i));
559 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
560 writel(((cs->size - 1) & 0xffff0000),
561 base + AHCI_WINDOW_SIZE(i));
565 static void ahci_mvebu_regret_option(void __iomem *base)
568 * Enable the regret bit to allow the SATA unit to regret a
569 * request that didn't receive an acknowlegde and avoid a
572 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
573 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
576 int board_ahci_enable(void)
578 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
579 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
584 #ifdef CONFIG_SCSI_AHCI_PLAT
587 printf("MVEBU SATA INIT\n");
589 ahci_init((void __iomem *)MVEBU_SATA0_BASE);
593 #ifdef CONFIG_USB_XHCI_MVEBU
594 #define USB3_MAX_WINDOWS 4
595 #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
596 #define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
598 static void xhci_mvebu_mbus_config(void __iomem *base,
599 const struct mbus_dram_target_info *dram)
603 for (i = 0; i < USB3_MAX_WINDOWS; i++) {
604 writel(0, base + USB3_WIN_CTRL(i));
605 writel(0, base + USB3_WIN_BASE(i));
608 for (i = 0; i < dram->num_cs; i++) {
609 const struct mbus_dram_window *cs = dram->cs + i;
611 /* Write size, attributes and target id to control register */
612 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
613 (dram->mbus_dram_target_id << 4) | 1,
614 base + USB3_WIN_CTRL(i));
616 /* Write base address to base register */
617 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
621 int board_xhci_enable(fdt_addr_t base)
623 const struct mbus_dram_target_info *dram;
625 printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
627 dram = mvebu_mbus_dram_info();
628 xhci_mvebu_mbus_config((void __iomem *)base, dram);
634 void enable_caches(void)
636 /* Avoid problem with e.g. neta ethernet driver */
637 invalidate_dcache_all();
640 * Armada 375 still has some problems with d-cache enabled in the
641 * ethernet driver (mvpp2). So lets keep the d-cache disabled
642 * until this is solved.
644 if (mvebu_soc_family() != MVEBU_SOC_A375) {
645 /* Enable D-cache. I-cache is already enabled in start.S */
650 void v7_outer_cache_enable(void)
652 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
653 struct pl310_regs *const pl310 =
654 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
657 /* The L2 cache is already disabled at this point */
660 * For Aurora cache in no outer mode, enable via the CP15
661 * coprocessor broadcasting of cache commands to L2.
663 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
664 u |= BIT(8); /* Set the FW bit */
665 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
669 /* Enable the L2 cache */
670 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
674 void v7_outer_cache_disable(void)
676 struct pl310_regs *const pl310 =
677 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
679 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);